This paper presents a methodology and software system architecture that enable conventional test equipment to take full advantage of embedded test structures implemented within the device under test. The proposed methodology provides a seamless transfer of embedded test related information from the design engineering to the manufacturing test environment, allowing for automated control of the embedded test for production go/no-go testing as well as advanced failure diagnosis.

A reconfiguration scheme is presented that is suitable for both yield and reliability enhancement of large-area VLSI implementations of binary tree architectures. The approach proposed makes use of partially global redundancy to allow clustered effects to be tolerated. The binary tree is cut a few levels above the leaves to form an upper subtree and many lower subtrees, with spare processors being grouped adjacent to the root of each lower subtree. Redundant links with programmable switches are used to permit reconfiguration. The cost of the scheme, in terms of redundant hardware, is comparable to that of other schemes. An O(N) H-tree layout is used. In comparison to existing schemes, the proposed scheme gives much better yield and better reliability.>