Accurate and fast system modeling is central to the rapid design space exploration needed for embedded-system design. With fast, complex SoCs playing a central role in such systems, system designers have come to require MIPS-range simulation speeds and near-cycle accuracy. The sophisticated simulation frameworks that have been developed for high-speed system performance modeling do not address power consumption, although it is a key design constraint. In this paper, we define a simulation-based methodology for extending system performance modeling frameworks to also include power modeling. We demonstrate the use of this methodology with a case study of a real, complex embedded system, comprising the Intel XScale embedded microprocessor, its WMMX SIMD co processor, L1 caches, SDRAM, and the on-board address and data buses. We describe detailed power models for each of these components and validate them against physical measurements from hardware, demonstrating that such frameworks enable designers to model both power and performance at high speeds without sacrificing accuracy. Our results indicate that the power estimates obtained are accurate within 5% of physical measurements from hardware, while simulation speeds consistently exceed a million instructions per second (MIPS).

The real-time execution of contemporary complex media applications requires energy-efficient processing capabilities beyond those of current superscalar processors. We observe that the complexity of contemporary media applications requires support for multiple forms of parallelism, including ILP, TLP, and various forms of DLP, such as subword SIMD, short vectors, and streams. Based on our observations, we propose an architecture, called ALP, that efficiently integrates all of these forms of parallelism with evolutionary changes to the programming model and hardware. The novel part of ALP is a DLP technique called SIMD vectors and streams (SVectors/SStreams) , which is integrated within a conventional superscalar-based CMP/SMT architecture with subword SIMD. This technique lies between subword SIMD and vectors, providing significant benefits over the former at a lower cost than the latter. Our evaluations show that each form of parallelism supported by ALP is important. Specifically, SVectors/SStreams are effective, compared to a system with the other enhancements in ALP. They give speedups of 1.1 to 3.4X and energy-delay product improvements of 1.1 to 5.1X for applications with DLP.

Accurate and fast system modeling is central to the rapid design space exploration needed for embedded-system design. With fast, complex SoCs playing a central role in such systems, system designers have come to require MIPS-range simulation speeds and near-cycle accuracy. The sophisticated simulation frameworks that have been developed for high-speed system performance modeling do not address power consumption, although it is a key design constraint. In this paper, we define a simulation-based methodology for extending system performance-modeling frameworks to also include power modeling. We demonstrate the use of this methodology with a case study of a real, complex embedded system, comprising the Intel XScale®g embedded microprocessor, its WMMX™ SIMD coprocessor, L1 caches, SDRAM and the on-board address and data buses. We describe detailed power models for each of these components and validate them against physical measurements from hardware, demonstrating that such frameworks enable designers to model both power and performance at high speeds without sacrificing accuracy. Our results indicate that the power estimates obtained are accurate within 5% of physical measurements from hardware, while simulation speeds consistently exceed a million instructions per second (MIPS).

The development of more processing demanding video standards on one hand and the popularity of mobile devices such as digital cameras or wireless videophones on the other hand introduce a need of optimization at the processor level. Reconfigurable systems provide an interesting answer to this problem and several works have explored the possibility of performance and power optimization. The following study focuses on tuning a reconfigurable hardware to the requirements of future media processing, using DSP operators appearing in recent FPGA families as an alternative to the typical ALU based architectures. In this paper, architecture perspectives are proposed with respect to low cost development constraints, backward compatibility, easy coprocessor usage and power / performance enhancement, using a new scalable data representation optimized for quality of service (matching pursuit 3D algorithms).

This paper compares the energy efficiency of chip multiprocessing (CMP) and simultaneous multithreading (SMT) on modern out-of-order processors for the increasingly important multimedia applications. Since performance is an important metric for real-time multimedia applications, we compare configurations at equal performance. We perform this comparison for a large number of performance points derived using different processor architectures and frequencies/voltages.We find that for the design space explored, for each workload, at each performance point, CMP is more energy efficient than SMT. The difference is small for two thread systems, but large (18% to 44%) for four thread systems. We also find that the best SMT and the best CMP configuration for a given performance target have different architecture and frequency/voltage. Therefore, their relative energy efficiency depends on a subtle interplay between various factors such as capacitance, voltage, IPC, frequency, and the level of clock gating, as well as workload features. We perform a detailed analysis considering these factors and develop a mathematical model to explain these results.Although CMP shows a clear energy advantage for four-thread (and higher) workloads, it comes at the cost of increased silicon area. We therefore investigate a hybrid solution where a CMP is built out of SMT cores, and find it to be an effective compromise. Finally, we find that we can reduce energy further for CMP with a straightforward application of previously proposed techniques of adaptive architectures and dynamic voltage/frequency scaling.

Image and video applications have been driving general- purpose processors (GPPs) and systems for more than a decade and will continue influencing the design of next generation architectures. In this paper we will first summarize the main characteristics of image and video applications compared to other workloads running on GPPs. Then we will give an overview of the recent changes and future trends in general purpose processor architectures to better handle image and video applications. First we will show that new SlMD (single instruction multiple data) features allow better exploitation of data-level parallelism and that media instructions have been added for some very specific algorithms. Another important aspect for image and video applications running on GPPs is the increasing memory latency compared to the processing time. In this context, the hardware prefetcher is slowly replacing software-prefetching instructions. In addition we will describe how additional support for multithreading like the newly introduced Intel Hyperthreading Technology or future multicore processors can benefit image and video applications. Finally we will explain how recently introduced frequency voltage scaling features can help to reduce power consumption for media applications due to their regular execution and fixed dead-line characteristics.

We address the problem of motion estimation (ME) in digital video sequences and propose a new fast, adaptive, and efficient block-matching algorithm. Higher quality and efficiency are achieved using a statistical model for the motion vectors. This model introduces adaptation in the search window, drastically reducing the number of positions where correlation-type computation is performed. The efficiency is further improved by progressively undersampling the macroblock. Patterns for undersampling are proposed to obtain the maximum benefit from single instruction multiple data (SIMD) instructions. In contrast with existing motion-estimation techniques, search strategy and subsampled patterns are closely linked. This shows that a good search strategy is much more important than blindly reducing the number of pixels considered for the matching pattern. We describe an implementation of the proposed matching strategy that exploits the very long instruction word (VLIW) and SIMD technology available in the new Itanium processor family. Results show that the proposed algorithm adapts easily to the evolution of the scene avoiding annoying quality drops that can be observed with other deterministic algorithms. The total number of operations required by the proposed method is inferior to those required by traditional approaches.

This paper characterizes selected workloads of multimedia applications on current superscalar architectures, and then it characterizes the same workloads on Intel hyper-threading technology. This technology enables multiple threads to run in parallel on a processor, by interleaving instructions from different threads in the pipeline. The workloads, including video encoding, decoding, and watermark detection, are optimized for the Intel Pentium 4 processor. Even if the workloads are very well optimized for the Pentium 4 processor, most of the modules in these well-optimized workloads cannot fully utilize all the execution units available in the microprocessor, due to the inherently sequential constitution of the algorithms. Some of the modules are memory-bounded, while some are computation-bounded. Therefore, hyper-threading technology is a promising architecture feature that allows more CPU resources to be used at a given moment. Our goal is to provide a better explanation of the performance improvements that are possible in multimedia applications using hyper-threading technology. We demonstrate different task partition/scheduling schemes and discuss their trade-offs so that the reader can understand how to develop efficient applications on processors with hyper-threading technology.

Media applications have been driving microprocessor development for more than a decade. Future multimedia applications will have much higher computational requirements. Indeed, tomorrow's PC experiences will be even richer in audio-visual effects, easier to use, and, more importantly, computing will merge with communications. Such application characteristics will differ from current application characteristics and thus, a new detailed analysis of such kernels is required. This paper proposes a selection of key kernels we believe will be prominent across applications running on future processors. An extensive study of these applications on current general-purpose processor architectures makes it possible to determine future media and communication characteristics and to identify bottlenecks that are not well addressed in current designs.

This paper presents the study and results of running several core multimedia applications on a simultaneous multithreading (SMT) architecture, including some detailed analysis ranging from memory-bounded kernels to computational-bounded functions. A performance metric to evaluate effective SMT performance gain is introduced, and compared to similar metrics on symmetric multiprocessor (SMP) systems. In addition, we analyze and compare SMT versus SMP systems, and highlight the advantages in the studied applications. The results indicate that sharing the cache in SMT processors can provide better cache locality and thus better performance although sharing the cache can introduce cache conflicts and reduce the actual cache size available for each logical processor. We also propose "mutual prefetching" -a technique to schedule threads so that they prefetch data for each other in order to reduce cache miss penalty.

For optimized MPEG video software encoders, data transfers in the memory hierarchy of current PC workstations is one of the main bottleneck. In order to hide the latency of memory loads, new instructions have been added to the latest generations of general purpose processors. We propose to model data prefetching in the memory hierarchy using Petri nets and to simulate the execution of MPEG encoding using a computer aided Petri net based simulation tool. The results show that the use of prefetching instructions for video encoding makes it possible to compensate for slower caches and for slower bus speed.

A new block matching (BM) algorithm for motion estimation (ME) is introduced in this paper. This algorithm is formed of two different steps: the first step considers, inside the search window, a fewer number of pixels rather than the full search algorithm (FSA); the second step considers a sub-sampled macroblock (MB) for the operations that contribute to determine the mean absolute difference (MAD). The sub-sampling technique is meant to exploit as much as possible the single instruction multiple data (SIMD) technique currently available on the most common general purpose processors. The overall number of operations needed to compute the BM is considerably reduced. The simulations results of the proposed algorithm compared with the conventional methods are given. The proposed technique shows an improvement in terms of number of operations required and for the PSNR and MPQM behavior, for MPEG2 encoded sequences.