To enable a globally integrated non-terrestrial network (NTN), the interconnection of heterogeneous low-earth orbit (LEO) satellite constellations via geostationary (GEO) relays is paramount. A significant challenge in this architecture lies in the dynamic allocation of hybrid free-space optical (FSO) and radio frequency (RF) links for the GEO-LEO interconnection. Conventional heuristic approaches that prioritize either instantaneous traffic demand or link visibility would be inadequate, as they fail to balance these conflicting metrics, resulting in performance bottlenecks and inefficient resource utilization. To resolve this allocation challenge, we propose a novel two-stage quasi-optimal control framework that maximizes the network-wide traffic accommodation rate. Our approach employs Binary Particle Swarm Optimization (BPSO) to solve the combinatorial FSO/RF link assignment problem, followed by convex optimization for RF bandwidth allocation. Simulation results demonstrate that our method consistently outperforms conventional approaches across various network loads, significantly improving the traffic accommodation rate and overall data throughput, thereby validating its effectiveness for dynamic resource management in hybrid satellite networks.

Low Earth Orbit (LEO) satellite constellation systems are expected to be integrated with terrestrial networks for future communication services over wide areas. For real-time applications, direct data relay between users is effective to minimize the propagation delay via LEO satellites, where multi-beam control is an essential function in LEO satellites to efficiently allocate beam resources over the areas. However, no previous works considered the satellite’s buffer limitations and the differences in throughput between uplink (UL) and downlink (DL) which caused queuing delays. This paper proposes a coordinated UL/DL multi-beam scheduling to minimize the end-to-end latency of data relay by considering the available buffer space of the satellite and variations in UL/DL throughput due to satellite movement. An optimization problem is formulated for the scheduling design to minimize the end-to-end latency. We demonstrate with simulation results that the proposed scheduling method reduces the latency by 16.0%, compared to the conventional methods.

The integration of satellite, aerial, and terrestrial networks in Satellite–Air–Ground Integrated Networks (SAGIN) enhances connectivity but also introduces new vulnerabilities to multi-layer jamming attacks. These attacks—originating from space-based, air-based, and ground-based sources—exhibit diverse signal characteristics, resource constraints, and durations, posing significant threats to communication performance and system security. A single mitigation technique is often insufficient to address these varied challenges effectively. In this paper, we propose a multi-layer adaptive jamming mitigation framework that dynamically adapts to the type of jamming encountered, with a particular focus on threats targeting Low Earth orbit (LEO) satellites within SAGIN. We evaluate a range of mitigation techniques and analyze their performance across different jamming scenarios. Our results show that tailored mitigation strategies are essential in SAGIN to achieve higher Signal-to-Noise Ratio (SNR) and lower Bit Error Rate (BER), highlighting the importance of jamming-aware defenses for enhancing the resilience and security of SAGIN systems.

For future network applications, ubiquitous connections and real-time cloud offloading are important paradigms for enabling important services. To achieve these goals, satellite networks, Free-Space Optical (FSO) communications, and Mobile Edge Computing (MEC) are key technologies. This paper proposes an efficient latency based task offloading strategy in a multi-tier Space-Air-Ground Integrated Network (SAGIN) with MEC and FSO communications. We consider a static deployment of ground users in Yamagata prefecture, Japan, offloading computational tasks to High Altitude Platforms (HAPs) and a Low Earth Orbit (LEO) satellite constellation. In this system, elevation-based FSO visibility and atmospheric attenuation can affect transmission latency, while server workload can impact computation latency. We design a hierarchical clustering-based framework and evaluate it alongside two other baseline approaches in terms of latency performance. Results show that our clustering-based task assignment achieves lower average latency and better load balancing, highlighting its potential for real-time edge-enabled FSO systems.

The use cases of satellite communications are rapidly expanding towards 6 G technology. Long propagation distances and dynamic changes in the network topology create an unstable environment with greater delays and disruptions than those of terrestrial networks. Delay/disruption-tolerant networks (DTN) have been developed to address these challenges. Since the nearearth satellite network is a scheduled network, contact plans can be created beforhand. Contact graph routing (CGR) is a contact-plan-based method used to determine the shortest path to deliver a bundle, a data unit of a DTN, to its destination. However, the conventional contact graph-based bundle transmission control methods do not consider the transfer order or bundle generation from multiple sources, such as observation satellites, ground, and marine users. Therefore, the bundle delivery ratio will decrease in future satellite networks, in which traffic of various sizes and acceptable delays are expected to flow in. In this study, we propose a bundle transmission control method for a multi-source DTN that considers the bundle variety. The simulation evaluation results demonstrated that the proposed method achieved a higher bundle delivery ratio than the conventional methods.

The scale of data centers has increased significantly in recent years, with their energy demands adversely impacting the environment. Consequently, distributed green data centers, equipped powered renewable energy, have gained considerable attention. However, conventional optical fibers installations for such data centers incur high costs and face locations constraints. Therefore, this study explores the use of optical satellite communications for distributed green data centers. Efficient task allocation is crucial to minimize service delays. However, task transmission time depends on satellite-ground link performance, while processing time is affected by the energy at data centers. Additionally, the non-linear relationship between the server per-formance and power consumption highlights the inefficiency, task allocation without future-aware considerations. To address this, we propose a method for task allocation and processing performance control that minimizes service delays through predictions of task generation, link performance, and power generation. In the proposed method, we formulate an optimization problem based on prediction data and find its solution by exploration. Simulations demonstrate that the proposed method significantly reduces tasks transmission and processing times.

We propose a free-space optical communication (FSO) system for terrestrial access networks that features a mechanism for adjusting optical beams to a wide angle, thereby forming a network with redundant communication paths to enhance reliability. To switch optical beams precisely among multiple neighbor nodes, we utilize liquid crystal on a silicon based spatial light modulator. We report the loss characteristics of the optical beam propagating in the atmosphere near the ground and then analyze the data transfer throughput over FSO using weather condition data of Yokohama city, Japan, which features a mild climate but also heavy rainfall and a few tropical storms every year. The results showed that the FSO network was able to maintain operation without any signal power shortages for error-free services during rainy conditions for one year when it had a link length of 320 m.

Recently, a fifth-generation cellular system (5G) is widely expected to provide plenty of wireless network resources (i.e., broadband capacity). In this paper, to validate 5G system performances, such as physical-layer and TCP-layer throughputs, we carry out a field trial at an actual indoor train station, named Haneda International Airport Terminal Station. In the field trial, we deploy the prototype 5G system (Central Unit, Distribution Unit, Radio Unit and 5G UE (tablet)) on the train station platform and evaluate mobile 5G downlink throughputs. Through the actual measurements, the results confirm that the prototype 5G system can achieve mobile broadband capacity (more than 1 Gbps) even when the UE is located anywhere at the indoor train station platform.

The “Internet of things” has become a common term, and low-power wide-area (LPWA) technology is attracting much attention as one of its elemental technologies. LPWA achieves wide-area communication without consuming much energy, allowing various data sensing and gathering applications. LoRa is an LPWA communication technology that uses unlicensed bands. Because it is possible to build a self-managed network with LoRa, many LoRa-based services will be scattered in the same area without an overall administrator. As a result, the communication performance of LoRa may degrade due to unintended radio interference. Unfortunately, many LPWA techniques, including LoRa, have low data rates, making it difficult to gather sufficient control information to avoid such degradation of communication performance. In this paper, we propose a method for estimating network congestion states through successive estimation using Bayesian updates of prior distributions. Computer simulations show the network state can be estimated by our proposed method with accumulating a little control information.

We present an analytic characterization of the steady-state throughput for end-users via optical cable systems when the signal-to-noise ratio (SNR) of the optical communication is given. Our model captures the effect of end-users' transmission control protocols (TCPs) and optical transport systems. We consider various TCPs, namely ultra-high-speed TCPs (UHS-TCPs), high-speed TCPs, and traditional TCPs. For the optical cable systems, we consider forward error correction (FEC), quadrature amplitude modulation, wavelength division multiplexing. We show that the robustness of UHS-TCP against errors enables cable systems to have an additional 2-dB SNR margin, which will provide extra capacity. The evaluation results show that total user throughput by UHS-TCP can be maximized when the optical communication enables some signal errors to remain for users, so-called post-FEC errors. Our model also predicts that the working 100-Tbps transpacific cable FASTER can be upgraded to 130 Tbps when it accepts a smaller margin for error-free service. Further, the model estimates FASTER will be able to provide 160-Tbps service when UHS-TCP is applied.

The sudden drop in the quality of an optical signal, called Q-drop, is an important factor for predicting network outages. Herein, we classify sudden drop events into two classes: one the results in a network outage, and one that does not result in a network outage, for the same period of time. Therefore, we build a predictor based on machine learning. The features of the predictor are given by characterizing the Q-drop event based on the optical layer characteristics immediately before the Q-drop event. The predictor is trained for each Q-drop event to adapt to the temporal change of the optical layer characteristics. Additionally, oversampling is applied to training data to avoid overlooking the network outage in the prediction. From the evaluation using real data, we showed that the proposed method is effective for the prediction of network outages in a short period. Furthermore, we found that information regarding the instability of the optical signal is important for the prediction of network outages. The result herein can contribute to improving the availability of the network because the proposed method predicts network outages based on characteristics that are invisible from the IP layer.

We developed an analytic characterization of the steady-state throughput of a free-space optical satellite communications (FSOSC) system which includes an ultra-high-speed transmission control protocol for FSOSC (TCP-FSO) and an adaptive- distributed-frame-repetition (ADFR) technique. Our model captures the effects of forward error correction (FEC) on optical transponders, overhead on an Ethernet link-up, error recovery on ADFR, and the congestion/retransmission controls of TCP. We conducted measurements using a testbed system including an FSOSC emulator. Our results validated our model estimates the throughput in FSOSC with sufficient accuracy. The model can estimate approximate throughput even in cases with many packet errors and large delay, for example, a 32% bit-error ratio (56% packet error ratio) and 500 millisecond round trip delay. Throughputs in various FSOSC conditions can be calculated easily with the model.

In this paper, we analyze the throughput of LoRaWAN Class-A data transfer with acknowledgement (ACK) under duty-cycle restriction which is imposed on gateways and end-devices. We show that ACK traffic limits the throughput of data traffic. We propose a method for aggregating ACKs from multiple users to improve the throughput and reliability of data transfer. The proposed method cumulates ACKs for multiple packets for multiple user-nodes. It also has schedules receive windows of user-nodes'. We show via performance analysis and simulation results that our method improves data transfer throughput by ten to thirty times.

To realize highly reliable video surveillance and provide ultrahigh-definition/immersive video streaming, it is planned to adopt the 5G cellular system using millimeter-wave (mmWave) as the wireless-network infrastructure. However, mmWave communication has a challenging issue: mmWave communication is extremely sensitive to obstacles, such as walls, pillars, and even human bodies, and this issue easily increases the packet loss rates and round trip time (RTT) (or disconnection from the base station) due to a no line of sight (NLOS) environment. Therefore, in this work, 5G throughput performances were evaluates in an indoor train station by considering the effect of an NLOS environment caused by blockage by human bodies. In addition, to improve the robustness of TCP transmission in a high-RTT and high-packet-loss environment (e.g., an NLOS environment), a state-of-the-art TCP, TCP-FSO, was used. In the evaluations, the MATLAB 5G library was used to simulate the 5G environment, and a Linux software-based network emulator, Traffic Control, was used to emulate the 5G network. From the evaluations, it the 5G mobile throughput characteristics were confirmed in three different crowded patterns (low, middle, and high density), and the TCP-FSO advantage against CUBIC-TCP was validated.

This paper describes a transmission control protocol (TCP) proposed for free-space optical communications (FSOC). FSOC has very high bit rates as an optic fiber communications method, but frequent FSOC signal errors, including burst error, can be a quite severe problem for ordinary high-speed TCPs. To achieve 10 Gbps or higher data transfer throughput on FSOC, the proposed TCP (designated "TCP-FSO") has new and improved features including multi-layer congestion control, retransmission control with packet loss point estimation, delay-based ACK congestion control, and ACK retransmission control. Obtained experimental results show that TCP-FSO achieves far higher data transfer throughput than other high-speed TCPs. For example, it achieved a thousand times higher throughput than the other high-speed TCPs in a real FSOC environment.

MuCCRA-Cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90nm CMOS process consisting of four dies each of which has a 4 × 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and the average execution time is reduced to 31% compared to that using a single chip.

The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfiguration power. Evaluation result shows that processing power for PEs is dominant and reconfiguration power is about 20.7% of the total dynamic power consumption. Based on the above evaluation results, we proposed two dynamic power reduction techniques: functional unit-level operand isolation and selective context fetch. Evaluation results demonstrate that the functional unit-level operand isolation can reduce up to 20.8% of the dynamic power with only 2.2% area overhead. On the selective context fetch, the power reduction is limited by the increasing of the additional hardware.

In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such contexts without wasting a context memory, we propose a new execution mode called instruction buffer mode in addition to the normal multi-context mode. In this mode, a configuration code from the central configuration memory is stored in the instruction buffer and executed directly. Furthermore, by exploiting a multicast method, a single configuration code loaded to the buffer can be executed by multiple processing elements in a SIMD fashion. We also investigate a mode selection policy based on simple formulas. From the result of implementation and evaluation by using a prototype DRPA called MuCCRA-1, it appears that the total execution time is reduced 12% by using the instruction buffer mode, while 12% of the semiconductor area is increased.

The configuration data transfer time of a dynamically reconfigurable processor often bottlenecks the hardware context switching time and degrades its computation performance. In order to reduce data transferring time from a central memory to hardware context memory modules in all processing elements (PEs) and switching elements (SEs), a multicasting mechanism called RoMultiC (row-muticast configuration) was proposed. However, the original Ro-MultiC used the whole PE or SE as a unit of multicast, the reduction of transfers is limited. Here, the trade-off between the granularity of multicast and hardware increase are evaluated, and the best way to make the multicast bit-map is explored. Evaluation results show that time for transfer is reduced up to 42% compared with the original RoMultiC with only 2% hardware overhead.

One of the benefits of coarse grained dynamically reconfigurable processor array(DRPA) is its low dynamic power consumption by operating a number of processing elements(PE) in parallel with low clock frequency. However, in the future advanced processes, leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage power, a fine grained Power Gating(PG) is applied to a DRPA, MuCCRA-2.32b, and leakage power and area overhead are measured. We evaluated the effect of two control modes; Pair and Unit Individual based on layout design and real applications. It appears that by applying PG for ALUs and SMUs in PEs individually, 48% of leakage power can be reduced with 9.0% of area overhead.

A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and translation lookaside buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.

In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are selectable. In this paper, we have generated various types of DRPAs and evaluated semiconductor area and speed by using the ASPLA/STARC 90-nm CMOS technology. From evaluation results, fundamental trade-offs between architectural parameters and area/delay are analyzed.

A new configuration scheduling algorithm in multicast configuration scheme is proposed and evaluated over reduction ratio of configuration data transfer cycles and power/energy overhead on a coarse-grained dynamically reconfigurable processor array (DRPA). As a case study, the proposed methods are applied to some real applications on a DRPA architecture MuCCRA-1. As a result, we confirmed that the proposed overwrite configuration technique for DRPAs reduced an application configuration cycles 66.5% at maximum compared to one without multicast and 20.2% compared to one without the overwrite configuration. It also decreased the configuration energy consumption 18.7% at maximum beyond the overhead of memory overwrites.

Dynamically reconfigurable processors improve the area-efficiency by executing a task with multiple hardware contexts. The maximum operational frequency is limited with a context which has the largest delay time, and it causes a certain overhead when each context has various delay time. A context dependent dynamic clock control method, which changes the clock so as to fit the current operational context, is proposed for NEC electronics' DRP-1. A clock generator consisting of a preset-able counter associated with the state transition table for controlling the context switching is proposed. Performance evaluation using several applications reveals that the proposed method improves the performance from 10% to 110% with a small increasing of the power consumption

In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the signal to noise ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long

Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

Multicontext reconfigurable processors can switch its configuration in a single clock cycle by providing a context memory in each of the processing elements. Although these processors have proven to be powerful in many applications, the number of contexts is often not enough. The context translation table which translates the global instruction pointer, or the global logical context number, into a local physical context number is proposed to realize a larger application while reducing the actual context memories. Our evaluation using NEC Electronics' DRP-1 shows that the proposed method is effective when the size of the tile is small and the number of context is large. In the most efficient case, the required number of contexts is reduced to 25%, and the total amount of configuration data becomes 6.9%. The template configuration method which extends this idea harnesses the power of multicontext devices by storing basic contexts as templates and combining them to form the actual contexts. While effective in theory, our evaluation shows that the return in adopting such mechanisms in more finer processors as the DRP-1 is minimal where the size of the context memory adds up relative to the number of processing units.

Dynamically reconfigurable processors with multi-context facility have been used for various applications. The relationship between context size and performance of such processors is analyzed based on real designs. The parallelism diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the performance is degraded about 23% when the size of a context becomes 1/2. The performance per cost is improved 7-14 times than that of the case without time-multiplexed execution.

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip.The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.

In some applications on dynamically reconfigurable processor (DRP), the input/output of data stream occupies about 20% of total execution time. In order to hide the overhead of input/output, the separation of the I/O context and double-buffering mechanism are proposed. Using the mechanism, I/O overhead of six streaming processing programs can be completely hidden. Based on the analysis of I/O performance, two alternatives for executing parallel processing with multiple DRP cores are compared and discussed.

Multi-homed environments are increasingly common, especially for mobile users. To efficiently utilize multiple access lines for single file transfer, multipath TCP communication methods have been proposed. A multipath TCP enables simultaneous distributed data transfer between two end-points on multiple TCP connections. However, these methods cannot fully utilize the available bandwidth of multiple paths because they do not properly consider the end-to-end delay of packet transmission, so out-of-order data arrival at a receiver causes a bottleneck in data sort operations. This problem is more severe in environments where the quality of each path is different or unstable, such as in wireless environments. To solve this problem, we propose a multipath TCP communication method that includes a data distribution method to enable in-order delivery at a receiver. We call this arrival-time matching load-balancing (ATLB). ATLB continuously calculates the delay of each path, including the TCP queuing delay at a sender and the network delay, and then sends a data segment through the TCP connection with the lowest end-to-end delay. Simulation results show that ATLB improves end-to-end throughput, especially in heterogeneous environments where the quality of paths differs. For example, ATLB enabled twice the throughput with the conventional multipath TCP. We also report performance evaluation results from our ATLB test bed system in a wireless network environment. Our ATLB test bed system was able to fully utilize the aggregate available bandwidth of unstable multiple wireless links.

Dynamically reconfigurable processor (DRP) developed by NEC electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the processing elements(PEs) and distributed memory modules, DRP-1 outperformed pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.

Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C67J3 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.