Resistive random access memory (RRAM) crossbar arrays enable analog in-memory computing, promising high parallelism and reduced data transfer for deep neural networks (DNNs) inference. However, when many columns share a single time-multiplexed analog-to-digital converter (ADC), readout latency, dominated by serialized conversion, can become a performance bottleneck. This article presents the First-Settle, First-Convert (FSFC) readout architecture, a readiness-driven ADC scheduling scheme for RRAM-based fully connected neural networks (FCNNs). Conventional crossbar readout relies on global settling, where all bitlines must wait for the slowest column to stabilize before sequential conversion begins. FSFC replaces this schedule with per-column readiness detection and a priority-queue encoder that continuously routes the earliest-settled column to the shared ADC, overlapping bitline settling and conversion without adding extra ADCs or changing the crossbar. Software experiments and SPICE-level circuit simulations in SkyWater 130 nm show that FSFC reduces inference latency by 35%–67% across 1- to 8-bit quantized MNIST FCNNs, with no loss of classification accuracy. A transistor-level implementation of the differentiator, hysteresis comparator, and digital priority-queue encoder incurs about 80 pJ of control energy per matrix-vector multiplication (MVM) for a$30\times 10$array, scaling to approximately 1 nJ per MVM and about 5%–8% tile area overhead for a 128-column tile. Because FSFC shortens ADC active time while introducing only modest peripheral circuitry, it provides a low-cost, drop-in latency improvement for RRAM compute-in-memory (CIM) tiles. The technique is orthogonal to existing ADC pooling, precision-reduction, and analog-cascading schemes, and can be integrated as a readout front-end in future crossbar-based accelerators.

This paper presents a radio architecture for 5G Vehicle to Everything (V2X) applications. A frequency planning suitable for the aforementioned radio architecture is proposed. A programmable Time-Interleaved (TI) Successive Approximation Register (SAR) Analog to Digital Converter (ADC) required for this radio architecture is presented. The effect of process and temperature (PT) variations on the performance of Monotonic SAR ADC is investigated. A calibration technique is proposed to account for PT variations in the Monotonic SAR ADC. Additionally, simulation results for TI SAR ADC designed in 22nm FDSOI which works at two different sampling frequencies for V2X applications are presented.

This paper presents a comprehensive analysis of hardware accelerators for neural networks in both the digital and time domains, where the latter includes spatially unrolled (SU) and recursive (REC) architectures. All accelerators are implemented and synthesized in a 65nm CMOS technology. An identical neural network model is implemented in the digital and time domain for comparative purposes in terms of throughput, power consumption, area, and energy efficiency. Post-synthesis results show that SU achieves the highest energy efficiency of 145 TOp/s/W with a throughput of 4 GOp/s. The digital core is the fastest among other cores, whereas REC is the slowest but is the most area-efficient, occupying 0.114 mm2. SU is more suited for applications with stringent power constraints and average performance, while REC is better suited for applications where the area is the most important requirement and the throughput is less significant. In contrast, the digital core is preferable for large neural networks and critical applications that require high performance.

This paper presents a single-stage power management unit to boost and regulate a low supply voltage for CMOS system-on-chip (SoC) applications. It consists of low-leakage, enhanced Dickson charge pump (DCP) that utilizes both stage and frequency modulation (FM) techniques to achieve high efficiency and lower area. In addition, the proposed design uses an enhanced stage-switch structure for the charge pump, which significantly reduces the cross-stage leakage. A stage number controller is used to control the gain of the charge pump by changing the number of stages based on the desired output voltage. FM is utilized to further fine-tune the output voltage through a closed-loop control based on a predetermined reference voltage. Silicon measurement results for the four-stage charge pump in 65-nm CMOS technology show a maximum end-to-end efficiency of 66% at an input voltage of 0.7 V and an output power of$27~\mu \text{W}$. The proposed design achieved more than a$100\times $reduction in leakage compared to traditional DCP. The system supports a range of load currents between 0.1 and$34~\mu \text{A}$with a maximum operating frequency of 1.8 MHz. The proposed system supports an input voltage range of 0.55–0.7 V which makes it an excellent candidate for solar and thermal energy-harvesting applications targeting low-power internet-of-things SOC.

This paper presents an area and power efficient multioutput switched capacitor (MOSC) DC-DC buck converter targeting ultra-low power and IoT devices. The MOSC converter has a variable input voltage range between 1.05V to 1.4V and generates regulated simultaneous multiple output voltage levels of 1V and 0.55V. Adaptive digital time multiplexing controller is employed to enable multiple power domains. In addition, a pulse frequency modulation is utilized to regulate the output voltages over a wide range of load current. The proposed converter supports a load current of 10μA to 350μA and to 10μA at a load voltage of 1V and 0.55V, respectively. Adaptive time multiplexing and pulse width modulation are implemented through a finite state machine to eliminate the reverse current issue. This problem arises during the switching from a low load voltage of 0.55V to a high load voltage of 1V. The MOSC circuit is fabricated in 65nm CMOS technology and it occupies an active area of 0.27mm2. Moreover, both MIM and MOS capacitors are utilized to further reduce the area of MOSC converter. Measured results shows that the peak efficiency of 78% is achieved at a load power of 300μW.

This paper presents a single stage power management unit that includes an enhanced stage-switch Dickson charge pump (DCP) to boost and regulate a low input voltage. A new switching mechanism is presented to significantly reduce the losses encountered in conventional DCP switches. Frequency and stage modulation are utilized in the proposed design. The stage modulation provides different gain levels (coarse) and the frequency modulation tunes the voltage level and regulates the output voltage based on a pre-determined reference voltage. Using four stages charge pump, silicon measurement results in 65 nm CMOS technology show a maximum efficiency of 66% at input voltage of 0.7 V and output power of 27 μW. The system supports a range of load current between 0.1 μA − 34 μA with a maximum operating frequency of 1.8MHz. The proposed system supports an input voltage range from 0.55 to 0.7 V which can be used in energy harvesting applications such as solar and thermal harvesting.

This talk will focus on an IoT Systems-on-Chip (SoCs) presented as an example of IoT work in the UAE and as part of the UAE SRC (Semiconductor Research Corp) Center of Excellence on Energy Efficient Electronic Systems (aka ACE4S http://www.src.org/program/grc/ace4s/) involving researchers from 5 UAE Universities looking at developing new technologies aiming at innovative self-powered wireless sensing and monitoring SoC platforms. The research targets applications in self-powered chip sets for use in public health, ambient intelligence, safety and security and IoT. ACE4S is the first SRC center of excellence outside the US. One such application, which we will discuss in details, is a ground breaking self-powered IoT SoC platform for wearable health care. More specifically we will present a novel fully integrated ECG signal processing system for the prediction of ventricular arrhythmia using a unique set of ECG features extracted from two consecutive cardiac cycles. Two databases of the heart signal recordings from the American Heart Association (AHA) and the MIT PhysioNet were used as training, test and validation sets to evaluate the performance of the proposed system. The system achieved an accuracy of 99%. The ECG signal is sensed using a flexible, dry, Graphene-based technology and the system is powered up by harvesting human thermal energy. The system architecture is implemented in Global foundries' 65 nm CMOS process, occupies 0.112 mm2 and consumes 2.78 micro Watt at an operating frequency of10 KHz and from a supply voltage of 1.2V. To our knowledge, this is the first SoC implementation of an ECG-based processor that is capable of predicting ventricular arrhythmia hours before the onset and with an accuracy of 99%.

A bio-potential amplifier intended for continuous monitoring of vitals characterized by its long operational lifetime is required to operate at the lowest power budget possible. Moreover, a compact active area directly related to portability is essential. This paper presents a 0.55pW auto gain controlled biopotential amplifier implemented in 65nm 1P7M CMOS for ECG signal classifier SoC. A chopper-stabilized amplifier is designed at 0.6V supply voltage to mitigate the DC offset and near DC flicker noise. The input ECG signal level is further set by the four gain levels of the variable gain amplifier (VGA) to provide maximum swing to the ADC. The whole system is integrated into a core are of 0.10mm2and can operate at a wide range of 0.6-1.2V supply voltage.

This paper presents an efficient thermal energy harvesting IC (EHIC) that supports a battery-less μWatt system-on-chips. The EHIC consists of an inductor-based DC-DC converter that boosts a low input voltage to a suitable output voltage level. Further, a switched capacitor buck converter is utilized to regulate the boost converter output voltage and to support multiple output voltage levels, namely 0.6V, 0.8V and 1V. In low energy mode and to enhance the efficiency, the EHIC is capable of bypassing the switched capacitor so that the load is driven directly from the boost converter. The prototype chip is fabricated in 65nm CMOS and occupies an area of less than 0.46mm2. Measured results confirm an efficiency of 65% at 0.6V output voltage and 42μW. In addition, the end-to-end peak efficiency is 71% at 0.8V output voltage and 182μW.

Electrocardiography (ECG) represents the hearts electrical activity and has features such as QRS complex, P-wave and T-wave that provide critical clinical information for detection and prediction of cardiac diseases. This paper presents a novel ECG processing architecture for the prediction of ventricular arrhythmia (VA). The architecture implements a novel ECG feature extraction which is optimized for ultra-low power applications. The architecture is based on Curve Length Transform (CLT) for the detection of QRS complex and Discrete Wavelet Transform (DWT) for the delineation of TP waves. Features extracted from two consecutive ECG cycles are used to set innovative parameters for VA prediction up to 3 hours before VA onset. Two databases of the heart signal recordings from the American Heart Association (AHA) and the MIT PhysioNet were used as training, test and validation sets to evaluate the performance of the proposed system.

This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112- ${\rm mm}^{2}$ area and consumed 2.78- $\mu \text{W}$ power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset.

This paper presents a novel implementation of the Maximally Stable Extremal Regions (MSER) detector on system-on-chip (SoC) using 65 nm CMOS technology. The novel SoC was developed following the Application Specific Integrated Circuit (ASIC) design flow which significantly enhanced its realization and fabrication, and overall performances. The SoC has very low area requirement (around 0.05 mm2) and is capable of detecting both bright and dark MSERs in a single run, while computing simultaneously their associated regions' moments, simplifying its interfacing with other image algorithms (e.g. SIFT and SURF). The novel MSER SoC is power-efficient (requires 2.25 mW) and memory-efficient as it saves more than 31% of the memory space reported in the state-of-the-art MSER implementation on FPGA, making it suitable for mobile devices. With 256×256 resolution and its operating frequency of 133 MHz, the SoC is expected to have a 200 frames/second processing rate, making it suitable (when integrated with other algorithms in the system) for time-critical real-time applications such as visual surveillance.

This paper presents a new fast and scalable Parallel Union-Find algorithm for image segmentation and its System-on-Chip (SoC) implementation using 65nm CMOS technology following the Application-Specific Integrated Circuit (ASIC) design flow. The algorithm is capable of labeling all foreground and background pixels, using the least possible pixels scanning. This contrasts the classical labeling algorithms that label only foreground (or background) pixels in a single run. The new algorithm utilizes only two memory blocks. In one memory block, it labels image segments using their seeds as the label and, simultaneously, the segments sizes are used as the other label in second memory block. By this parallel labeling, monitoring the image segments is very fast and efficient. With 350 MHz operating frequency, the processing rate estimated to be 2100 frames/sec, the total chip area of 15950.5 μm2 (off-chip memory) and very low-power of 0.3 mW, the SoC tends to be an excellent candidate for mobile devices and real-time applications.

The paper presents a novel technique to segment and extract streets from satellite images. This technique utilizes, for the first time in the known literature, the Maximally Stable Extremal Regions (MSER) algorithm to robustly identify and segment streets from satellite images. The technique extracts dark MSERs and then classifies them based on multiple metrics such as the intensity of the pixels, the region stability, and the major-to-minor axes ratio. Testing results under multiple scenarios corroborate the accuracy of the proposed technique. The technique will allow fast and accurate implementation of a wide spectrum of applications such as in Global Positioning System (GPS) driving guidance.

This paper presents a real-time adaptive ECG detection and delineation algorithm alongside an architecture based on time-domain signal processing of the ECG signal. The algorithm is enhanced to detect large number of different P-QRS-T waveform morphologies using adaptive search windows and adaptive threshold levels. The proposed architecture has been implemented in the state-of-the-art 65-nm CMOS technology. It occupied 0.03416 mm2 area and consumed 0.614 mW power. Furthermore, the non-complex nature of the architecture resulted with a realization using smaller number of computation and higher performance. The design of the QRS detector was tested on ECG records obtained from the Physionet QT database and achieved a sensitivity of Se =99.83% and a positive predictivity of P+= 98.65%. Similarly, the mean error values of the T peak, T offset, P peak and P offset were found to be -1.367, 6.36, 5.5 and -2.59 milliseconds, respectively, using the same database. The small area, low power, and high performance of our architecture makes it suitable for inclusion in System On Chips (SOCs) targeting wearable mobile medical devices.

ECG intervals such as QRS, QT and PR provide significant information and are widely used as clinical parameters for diagnosing cardiac diseases. This paper presents a novel QRS detection technique based on Curve Length Transform (CLT) and a refined delineation of P-wave and T-wave using Discrete Wavelet Transform (DWT). The proposed technique was verified using the PhysioNet database. The QRS detection achieved a sensitivity of 98.59% and a positive predictivity of 97.86%. The QRS duration, QT interval and PR interval had a mean error of -1.56± 28.8ms, -5.39± 42.4ms and 0.86± 40.3ms respectively. The proposed algorithm is computationally efficient and is simpler to implement in hardware, hence, will lead to a faster execution time, smaller design area and consequently low power consumption.

This paper introduces a dramatically novel traffic signs recognition (TSR) system that can perform traffic sign detection and tracking simultaneously. The proposed approach utilizes intensity images and the depth images, in parallel, to robustly detect and track traffic signs in real-time. Additionally, we suggest to supplement the ordinary traffic signs with the corresponding quick-response (QR) code plates that inherent the many advantages of the QR-codes, introducing the concept of QR-TSR systems.

Wafer defects, which are primarily defective chips on a wafer, are of the key challenges facing the semiconductor manufacturing companies, as they could increase the yield losses to hundreds of millions of dollars. Fortunately, these wafer defects leave unique patterns due to their spatial dependence across wafer maps. It is thus possible to identify and predict them in order to find the point of failure in the manufacturing process accurately. This paper introduces a novel simplified subspaced regression framework for the accurate and efficient identification of defect patterns in semiconductor wafer maps. It can achieve a test error comparable to or better than the state-of-the-art machine-learning (ML)-based methods, while maintaining a low computational cost when dealing with large-scale wafer data. The effectiveness and utility of the proposed approach has been demonstrated by our experiments on real wafer defect datasets, achieving detection accuracy of 99.884% and R2of 99.905%, which are far better than those of any existing methods reported in the literature.

This paper comprises two new methodologies to improve yield and reduce system-on-a-chip power. The first methodology is based on faulty static random-access memory (SRAM) cells detections and cache resizing. The key advantage of this approach is that it enables the end user to control the system's parameters to be error tolerant. Furthermore, this technique enables aggressive voltage scaling which causes parametric (soft) failures in SRAM-based memory. As such, the proposed methodology can be utilized to exchange cache size for lower power or better yield. In the second methodology, data from faulty cells are treated as imposed noise. Depending on the application, this error percentage (imposed noise) can be mitigated through three options. First, ignore error if the percentage of the error is tolerable. Second, simple hardware filtration is needed. Finally, software-based filtration is required. The viability of this approach is that it allows aggressive voltage scaling below the traditional to be a 100% correct approach for SRAM supply, which results in substantial reduction of power, trading off quality for power. For both approaches, BIST is used as part of the powerup sequence to identify the faulty memory addresses per voltage level and compute the faulty cells percentage. Furthermore, the proposed methodologies help in improving reliability and counteracting long-term effects on memory cell stability and lifetime degradation caused by negative bias temperature instability.

A charge pump (CP) design that simultaneously reduces current mismatch and sensitivity to process, voltage, and temperature variations is presented. The self-biased and self-regulated circuit uses a dual-feedback mechanism with a replica CP to dynamically stabilize and equalize the currents over a wide output voltage range under varying operating conditions. The circuit is further analyzed and designed in 90-nm CMOS. Extensive corner and Monte Carlo runs are used to verify its current matching capabilities as well as its stability and response within a phase locked loop. The CP achieves near perfect current matching for a wide output voltage range and for temperatures ranging from -30 °C to 90 °C and a power supply between 1.08 and 1.32 V.

Network-on-chip (NoC) communication architectures are emerging as the most scalable and efficient solution to handle on-chip communication challenges in the multicore era. In NoCs, power estimations in the early stages of the design help the designers to optimize the design for energy consumption and efficiently map applications to achieve low-power solutions. However, in 90-nm designs or below, the impact of parasitics not only influence timing closure, but also leads to variability in power and area budgets among different NoC architectures. There is a growing need for advanced design methodologies to overcome these issues in NoC designs. This paper presents a system-level design methodology based on layout and power models to achieve low-power and high-performance NoC designs. The impact of global interconnects with and without repeater insertion on the bandwidth and power is considered. Width and spacing of global interconnects and its effect on performance and power dissipation are analyzed. For architectural-level power analysis, different router designs for Chip-Level Integration of Communicating Heterogeneous Elements (CLICHE), Butterfly Fat Tree (BFT), Scalable, Programmable, Integrated Network (SPIN), and Octagon NoC architectures are implemented using ARMs 65-nm standard cell library in 65-nm Taiwan Semiconductor Manufacturing Corporation (TSMC) process. The router designs are synthesized in RVT process using a ${V}_{\rm dd}$ of 1.0 V and a temperature of 25$^{\circ}{\rm C}$ . Synopsys Prime Time-PX design tool is used for calculating average power dissipation of the router designs.

Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata) satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the αdataequals 0.2 and the activity factor of the control signals is equal to 1/64 of the αdata. The total metal resources required to implement Asynchronous design is decreased by 12%.

Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch links and repeaters for BFT represents only 1% of the total power dissipation of the network. In addition of providing high throughput, the BFT is a power efficient topology for NoCs.

This paper describes a new course on mixed-signal IC test engineering, jointly established by the Department of Electrical and Computer Engineering (ECE) of The Ohio State University and Texas Instruments. The course is motivated by the lack of qualified test engineers in industry and the absence of this education at the collegiate level. The course objective is to help student obtain the fundamental skills required for a mixed-signal IC test engineer. The course structure and laboratory developments are covered in details. Students feedbacks based on anonymous survey indicate that the goals are well met.

This paper presents a resistor-free temperature compensated CMOS current reference designed in a standard 0.18 μm CMOS process. The temperature compensation scheme is achieved by combining a PTC (Positive Temperature Coefficient) current generator circuit with a NTC (Negative Temperature Coefficient) current generator circuit. The proposed design is shown to be less sensitive to process and temperature variations and well suited for integration into other circuits as an accurate and stable current source. Simulation results for the proposed current reference show a temperature coefficient of 170 ppm/°C over a temperature range of 20 °C to 120 °C and an output current variation of 3% over a power supply range of 2 V to 3 V.

The IIP2 requirement in fully integrated direct-conversion receivers using FDD duplexing is prohibitively high and demands the use of an external filter in order to attenuate the leakage from the transmitter. This paper presents a digital calibration technique for passive CMOS down-converters that allows a direct conversion receiver achieve the requirements without external filtering. A Least-Mean-Square optimization algorithm is used in order to reduce the low-frequency second-order intermodulation product. The algorithm controls the digital calibration structures at the biasing of the passive mixer and adapts them until the second order intermodulation drops below the noise level. The method is tested by calibrating a 1.2-V 65nm CMOS passive mixer targeting UMTS/LTE applications at several corner conditions including worst case mismatches in the switching pairs.

In this work, we present a wideband CMOS RF amplitude detector for on-chip self-test and calibration. The high conversion gain detector enables accurate on-chip amplitude measurements and allows for accurate transceiver parameter prediction. The detector operates from 500MHz to 9GHz while detecting signal amplitudes from 0 to 0.7V with a sensitivity of -10V/V. Several test cases are presented to demonstrate the functionality of the design and its ability to detect key RF block parameters such as gain, distortion, and phase mismatch. The detector is built in 0.18μm CMOS and consumes less than 0.8mW from a 1.8V power supply.

This paper presents a comparative study of ΣΔ modulators for use in fractional-Nphase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.

High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

RFIC design using low-voltage nanometer CMOS technologies offers both advantages and challenges. This paper describes the limitations of using these technologies in receiver front-end design and proposes circuit solutions. Several techniques such as wideband noise reduction, inductoreless peaking, passive mixing, and low flicker noise amplification are reviewed and employed. A receiver front-end that covers 700 MHz-6 Ghz and supports the WiMAX/LTE standards is designed based on these circuit solutions. The front-end is designed using 1.2 V 90 nm CMOS and consumes a total power of 10.2 mW. The total gain is 32 dB, noise figure is 4 dB, flicker noise corner is 10 kHz, and third order intercept point is -10 dBm/0 dBm.

This paper presents a new digital calibration technique that allows CMOS Gilbert cell down-conversion mixers to meet their block specifications under large process, temperature and power supply variations. The gain and IIP3 are calibrated by regulating the current of the input differential pair and by switching the loads. IIP2 calibration is achieved by using a novel technique that consists of offset voltages cancellation in the switching pairs. The technique is tested by calibrating a 0.18um CMOS mixer in several corner conditions. It is found that by using this calibration technique, the Gilbert cell mixer can achieve yields comparable to digital circuits, hence making it amenable to AMS SoC integration.

An analog adaptive equalizer based on feed-forward architecture is implemented on 0.18μm digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125Mbps over UTP CAT-5 cable of up to 100m length. Novel low-voltage, low-power circuit techniques resulted in 3.7mW total power consumption and supply voltage operation as low as 1.6V. This is over 3times power savings and 0.4V reduction in supply voltage from previously reported implementations on the same process node. The minimum horizontal eye opening of the equalizer (including the transmit path driver) under all cable length is 0.67 UI and the total area of the equalizer is 27738μm2.

In this paper, we present the design and implementation of the RF front-end for the WiMAX (802.16e) and WLAN (802.11n) standards. The front-end covers the frequency ranges of operation for licensed and unlicensed bands of WiMAX and WLAN, which include 2.3 GHz - 2.9 GHz, 3.3 GHz - 3.7 GHz and 4.9 GHz - 5.9 GHz. The gain of the front-end is between 30 - 32 dB for all the bands while achieving noise figures of 2.5 dB, 3.5 dB and 5.9 dB at the center frequencies of the lower, middle and upper bands respectively. The total front-end operates at the bias current of 26.25 mA and consumes 48 mW of power. The components include in the front-end are low noise amplifier, active balun or single to differential converter and mixer. The design of the front-end is performed in 1.8 V IBM CMOS 0.18mum process

This paper investigates the application of Active Noise Cancellation (ANC) techniques in improving the performance of sigma delta ADCs. Using a specific technique of ANC, adaptive line enhancer (ALE), quantization noise of sigma delta modulator can be reduced significantly and signal to noise ratio is boosted. Mathematical model of this system in steady state is presented. Simulation results on different sigma delta ADCs are very promising and show significant improvements in signal to noise ratio and spurious free dynamic range. ALE processes the signal at the output of sigma delta modulator; hence, it will be a part of digital post-processing of the signal and no analog complexity will be added to the converter by using this technique.

In this paper, the design and performance of a CMOS fifth-order low-pass anti-aliasing filter for baseband mobile communication are presented. Based on a differential difference amplifier (DDA), a novel fully-differential Sallen-Key filter is realized. This fifth-order filter operates at a supply voltage of 3 V and has a cutoff frequency of 19 MHz. It provides up to 1 V differential output with 0.03% total harmonic distortion (THD) and dissipates only 4.5 mW. The input IP3 is +39 dBm, and the input-referred noise in the passband is 60 nV//spl radic/(Hz).

The statistical design of the four-MOSFET structure and the 10-bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in both circuits is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuits are fabricated through the MOSIS 2 /spl mu/m process using MOS transistor Level-3 model parameters. The experimental results are included in the paper.

In this paper, a novel CMOS bandpass filter working at 900 MHz is proposed. Through a new high-Q active inductor, this design avoids the use of expensive external or on-chip inductors. Designed in AMS 0.35 /spl mu/m, simulation results in Cadence show that this fully differential bandpass filter can achieve high-Q and tunable central frequency with low power consumption.

In this paper, a low noise amplifier suitable for wireless WCDMA systems is designed with AMS 0.35 /spl mu/m CMOS process. A biasing circuit with temperature compensation is presented. The simulation result in Cadence shows that the LNA can achieve 12.7 dB power gain and 1.7 dB noise figure with 7 mW power consumption at 27/spl deg/C. The gain and NF variations over -45/spl deg/C to 85/spl deg/C are less than 0.4 dB and 0.1 dB respectively.

In this paper, the design and performance of a CMOS baseband circuit for WCDMA direct conversion receiver are presented. Consisting of one 5th-order anti-aliasing filter, one 4th-order tunable channel filter, and three variable gain amplifier (VGA) stages, the baseband chain provides 72dB gain range with 2dB gain step and is tunable to select three different bandwidths (from 5MHz to 20MHz radio-frequency spacing). It dissipates only 18mW from a single 3V supply. The input IP3 is 10dBm, and the input-referred noise in the passband is 41nV/$\sqrt{Hz}$.

A modified architecture of the second-order switched capacitor modulator is proposed. A simple four-transistor variable gain attenuator is included in the architecture which continuously adjusts the reference voltage of the quantizer feedback. This improves the output SNR for small signal input and reduces the harmonic distortion for large signal input. Simulation results show that it achieves higher dynamic range and lower harmonic distortions compared with the traditional architecture.

A low-voltage (/spl les/3 V) CMOS four quadrant multiple is introduced which has an almost rail-to-rail differential-input-swing with a low signal-distortion (/spl les/1% for 100 kHz signal). The proposed circuit is composed of a pair of rail-to-rail differential-input V-I converters and a pair of voltage-followers. This topology of multiplier results in a high frequency capability with low power consumption. In a 1.2 /spl mu/m n-well CMOS process, the 3 dB frequency of the multiplier is in a range of 103 MHz. Measured total power consumption is around 0.52 mW with supply voltage 2 V. The multiplier can operate at a minimum supply voltage of 1.8 V.

Two transconductors composed of two square-law CMOS cells are introduced in this paper. The analysis of the cells is given. The transconductors operate in the saturation region with a fully balanced input signal. Simulations were done for 0.8 /spl mu/m n-well process using BSIM3 model parameters. The first circuit has a trade-off between low voltage operation and low power dissipation. The circuit has a cutoff frequency of 170 MHz and P/sub dis/=1.17 mW for a bias current of 120 /spl mu/A. The second transconductor has aimed to overcome the trade-off and to improve the performance; the circuit has a cutoff frequency of 236 MHz and P/sub dis/=1.74 mW for the same bias current; however, it is possible to reduce the bias current, since the trade-off the transconductors have a THD of less then -56 dB and -60 dB, respectively, for 1 MHz, 0.5 V peak-to-peak sinusoidal input. A comparison between the two circuit performances is given.

This paper describes a new technique for realizing CMOS digitally controlled, dB-linear variable gain amplifier (VGA) circuit. The circuit is developed taking into account system level issues for a direct conversion receiver. Besides being effective and simple to use from a system point of view, the developed VGA offers precise gain control, high linearity and low power consumption. The circuit can operate in a current domain or a voltage domain mode with single ended or fully differential signal handling capability. The proposed VGA circuit is implemented using a novel class AB operational transconductance amplifier and current division networks. Simulation results are included.

The design and performance of a rail-to-rail low-voltage CMOS fifth-order elliptic low-pass GM-C filter for baseband mobile communication are presented. The operational transconductance amplifier (OTA) used in this filter is a low-voltage rail-to-rail voltage-to-current converter (V-I converter). In this V-I converter, an N-type V-I converter cell is connected in parallel with its counterpart, a P-type V-I converter cell, to achieve common-mode (CM) rail-to-rail operation. Two maximum-current selecting circuits and an output current subtraction circuit are utilized to generate constant-g/sub m/ output currents for this OTA. This fifth-order elliptic low-pass GM-C filter operates at a supply voltage of 3 V and has a cutoff frequency of 280 to 405 kHz. It provides up to 700 mV/sub pp/ output with 1% total harmonic distortion (THD), dissipates 2.48 mW at V/sub cm/=1.5 V, and occupies 1.62 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.

This paper discusses the use of common source MOS transistors operating in the linear region to create four-quadrant multipliers. Analyses of two different multipliers based on this concept are presented and verified through SPICE simulations. The second circuit is shown to have low distortion, low sensitivity to mismatch, and good high frequency performance.>

This paper introduces three highly linear single-capacitor MOSFET-C integrators for use in continuous-time filters. Only one capacitor per integrator is required to achieve complete cancellation of MOS nonlinearities. A fifth order lowpass Chebychev filter based on the design of the new integrators has been fabricated using a 2 micron CMOS process. The design procedures and experimental results from the fabricated chip are presented.>

This paper describes a simple test structure for accurately determining the properties of any resistor structure for a given process. Experimental results are given for p-type diffused resistors in a p-well process, and n-type diffused and poly resistors in an n-well process in order to illustrate the extraction procedure and the level of accuracy achieved.>

In this paper, we present a statistical constrained CAD-compatible optimization algorithm for analog MOS integrated circuit design. The algorithm uses design of experiments (DOE), together with the response surface methodology (RSM), to determine simple empirical models relating circuit performances to device sizes. It then applies the Lagrange multiplier method to solve the resulting statistical constrained nonlinear optimization problem. The algorithm is guaranteed to converge to the global minimum. Using this new algorithm, we show that the transistors which cause variations in the performances of a two-stage op-amp can be identified and resized in an area-efficient manner to meet performance specifications.>