This paper first summarizes the complete range of analog defects and resultant faults. A complete set of metrics is then derived for measuring the quality of analog tests. The probability-based equations for fault coverage, defect level, yield coverage, and yield loss are self-consistent, and consistent with existing equations for digital test metrics. We introduce the concept of partial coverage, show that it is inherent to analog testing, and show that coverage cannot be calculated without knowing the performance specifications for a circuit, as well as the process parameter distributions. Practical methods for calculating probabilities are discussed, and simple, illustrative examples given.

In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in a hierarchical manner. The effects of parameter variations in one level of design hierarchy on those of the next are mapped through linear and piecewise linear sensitivity functions. The models allow computation of the statistical distributions of the circuit parameters and their correlations. This data is used to determine the critical circuit specifications that must be measured and those that may be eliminated from the testing process.

While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. The primary difficulty in analyzing signatures for analog signals is that the latter are imprecise in nature. Therefore, deterministic signature analysis schemes, such as those based on finite-field arithmetic using linear feedback shift registers, are unsuitable for analog circuits. In this paper, a novel signature analysis scheme for analog and mixed signal circuits is proposed. The signatures possess the interesting property that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold; the larger the effects of the failure, the larger the difference between the generated signature and the expected signature. The probabilities of aliasing and false rejection are also derived. Results for an example filter circuit are presented.

An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise. The coefficients of the polynomial are translated into offset, gain, and harmonic distortion for an analog-to-digital converter (ADC) driven by a digital-to-analog converter (DAC) or other appropriate signal source. The algorithm is efficient enough to be implemented as a built-in self-test for an IC, and is particularly suitable for sigma-delta converters.

In this paper an efficient low-cost built-in self test (BIST) scheme is proposed for analog circuits. The key idea is to use rectangular pulses of random widths obtained directly from a digital linear feedback shift register to perform transient testing of the circuit under test. A small amount of synchronization and comparison circuitry is necessary to perform the BIST. A methodology for designing the BIST hardware is described and results are discussed. The method is seen to be both efficient and low cost.

While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. In this paper, a novel signature analysis scheme for analog and mixed-signal circuits is proposed. The signatures possess the interesting properly that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold.>

The areas of analog circuit fault simulation and test generation have not achieved the same degree of success as their digital counterparts owing to the difficulty in modeling the more complex analog behavior.We present a novel approach to this problem by mapping the circuit and circuit-level faults to the dis- crete domain.An efficient fault simulation is then performed on this discretized circuit for the given input test waveform.

Recognizing that specification testing of analog circuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique. With the help of hierarchical fault models for parametric and catastrophic faults, and a very efficient fault simulator, our simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits. By a suitable choice of parameters in the test generator, we can either determine the best test (maximize the error between the good and the faulty responses) for every fault (resulting in a large test set), or generate the smallest test set for all the faults. Finally, fault coverage values provide a quantitative evaluation of the final test set.

This paper presents an efficient unified approach to mixed-signal fault simulation. A common fault simulation platform is developed for continuous valued analog circuits, discrete time switched-capacitor circuits and binary valued digital circuits, by discretizing the analog circuit, using discrete models of switched-capacitor circuits and complementing the stuck-at digital fault models with comprehensive behavioral analog fault models.>

Presents a comprehensive approach, based on functional error characterization, for modeling faults in analog and mixed-signal circuits. A case study based on a CMOS and an nMOS operational amplifier is discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level.>

Delay fault testing of iterative arithmetic arrays (IAAs) is important because IAAs contain long critical paths and often determine the clock speed. A new approach, based on a weighted graph model has been developed that exploits the regularity of IAAs to select paths to be tested, and generates delay fault tests for those paths. The number of longest paths in an IAA grows exponentially with the dimension of the IAA, but the technique tests only a selected subset of longest paths, whose size is linear in the dimension of the IAA. A Monte-Carlo simulation was performed to ascertain the detection of delay faults in paths that were not explicitly tested. Promising results were obtained.>