We present a new approach to circuit comparison which was developed to combine general applicability with most of the advantages of hierarchical processing. The basic principle of operation is the pattern matching of arbitrary subcircuits in larger circuits. Typically, a hierarchical schematic has to be compared with a flat netlist extracted from the layout. In our approach, this is accomplished by successive, bottom-up matching of schematic cells in the layout netlist, thus reconstructing the schematic hierarchy. The method is independent of circuit technology and design style. A sophisticated hierarchy handling scheme enables the usage of ill-structured schematic hierarchies. The typical problems in circuit comparison are overcome in a quite natural way by pattern matching. Real-life examples indicate the tool's suitability in function and performance. The hybrid approach is a mixture between the pattern matching approach and the traditional refinement technique. In this way, the advantages of both methods can be exploited.>

The authors present a novel approach to circuit comparison and building-block recognition. In contrast to conventional systems, netlist pattern matching is employed as the basic principle, making it possible to identify arbitrary subcircuits in larger circuits. Typically, a hierarchical netlist derived from a schematic and a flat netlist extracted from a layout have to be compared. In the present approach, this is accomplished by the successive (bottom up) matching of the schematic cells in the layout netlist, thus restoring the schematic hierarchy. The pattern matching algorithm is embedded in a sophisticated hierarchy handling scheme, making it possible to process even ill-structured hierarchies. The method is independent of circuit technology and design style. Typical drawbacks of traditional systems such as the handling of parallel paths or the permutability of (groups of) terminals are overcome in a quite natural way. Additionally, the proposed approach offers a universal and flexible solution to the problem of functional but not too topological isomorphic subcircuits. Real-life examples prove its suitability in function and performance.>