Demo Data from EDBT 2026 / reviewers in the wild / expert
Yu Zhang 0294
dblp:50/671-294
· DBLP profile ↗
2ranked-venue papers
2as first author
2since 2021 · last 2026
0009-0008-0018-0810ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 60% Storage systems · 40% | |
| Network and information security
1 paper |
Hardware security and side channels · 50% Cryptographic primitives and cryptanalysis · 50% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory management › virtual memory
address translation |
1.0 | 1 | 2026 | HyTorC: Hybrid Address Translation for SSDs Supporting Compression · ACM Trans. Storage 2026 |
Storage systems › flash and SSD › flash memory management
flash translation layer |
1.0 | 1 | 2026 | HyTorC: Hybrid Address Translation for SSDs Supporting Compression · ACM Trans. Storage 2026 |
Storage systems › flash and SSD
solid-state drive |
1.0 | 1 | 2026 | HyTorC: Hybrid Address Translation for SSDs Supporting Compression · ACM Trans. Storage 2026 |
Hardware security and side channels › memory integrity
memory integrity verification |
0.9 | 1 | 2025 | DCAS-BMT: Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree for Performance Enhancement in Secure Non-Volatile Memory · IEEE Trans. Computers 2025 |
Cryptographic primitives and cryptanalysis › hash functions
merkle tree |
0.9 | 1 | 2025 | DCAS-BMT: Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree for Performance Enhancement in Secure Non-Volatile Memory · IEEE Trans. Computers 2025 |
Memory systems
non-volatile memory |
0.9 | 1 | 2025 | DCAS-BMT: Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree for Performance Enhancement in Secure Non-Volatile Memory · IEEE Trans. Computers 2025 |
Memory systems › non-volatile memory
secure non-volatile memory |
0.9 | 1 | 2025 | DCAS-BMT: Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree for Performance Enhancement in Secure Non-Volatile Memory · IEEE Trans. Computers 2025 |
Memory systems
data locality |
0.3 | 1 | 2025 | DCAS-BMT: Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree for Performance Enhancement in Secure Non-Volatile Memory · IEEE Trans. Computers 2025 |
Methods — techniques the papers use, named apart from their topics
simulation · 1.7run-length encoding · 1.0bitmap compression · 1.0background scrubbing · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | HyTorC: Hybrid Address Translation for SSDs Supporting CompressionabstractHigh-capacity solid-state drives (SSDs) with expected capacities of one PByte and more will address cloud storage and archiving environments previously dominated by magnetic disks. These new applications are very cost-sensitive, so unnecessary overhead must be reduced as much as possible without sacrificing the performance advantages of SSDs. An expensive component within a scale-up SSD is the on-device memory to map host logical page numbers to flash pages. This article, therefore, proposes HyTorC, which builds on the idea of S-FTL to represent sequentially stored logical pages using bitmaps instead of providing one entry per logical page. HyTorC extends this idea by introducing, for the first time in an FTL, compression of these bitmaps using run-length encoding, and by investigating the effects of background scrubbing to realign randomly written pages into contiguous runs. This background scrubbing allows HyTorC to keep large portions of the mapping table in block mapping mode, further reducing the memory footprint. HyTorC retains the flexibility of the page mapping scheme and supports compression of logical blocks within the SSD, allowing multiple compressed logical pages to be stored within a single physical page. HyTorC is fully implemented in an open-channel SSD. Our tests show that HyTorC can reduce memory consumption by an average of 98.9% over standard page mapping, 95.6% over the DFTL scheme, 87.3% over S-FTL, and 56.5% over the learned index-based approach LeaFTL for the Alibaba Cloud block traces, and by 98.6% over standard page mapping, 95.5% over the DFTL scheme, 84.1% over S-FTL, and 61.5% over LeaFTL for the Microsoft Research Cambridge traces. HyTorC focuses on the memory footprint of the FTL and not on performance. However, the performance evaluation shows that HyTorC achieves similar performance compared to page mapping and FTLs based on learned indexes. Yu Zhang 0294, Renhai Chen, Gong Zhang 0001, Peng Wang 0037, Xin Yao 0008, Keji Huang, André Brinkmann |
ACM Trans. Storage | 1 |
| 2025 | DCAS-BMT: Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree for Performance Enhancement in Secure Non-Volatile MemoryabstractTraditional DRAM-based memory solutions face challenges, including high energy consumption and limited scalability. Non-Volatile Memory (NVM) offers low energy consumption and high scalability. However, security challenges, particularly data remanence vulnerabilities, persist. Prevalent methods such as the Bonsai Merkle Tree (BMT) are employed to ensure data security. However, the consistency requirements for integrity tree updates have led to performance issues. It is observed that compared to a secure NVM system without persistent secure metadata, the average overhead for updating and persisting the BMT root with persistent secure metadata is as high as 2.48 times. Therefore, this paper aims to mitigate these inefficiencies by leveraging the principle of memory access locality. We propose the Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree (DCAS-BMT). The DCAS-BMT is dynamically built and continuously adjusted at runtime according to access weights, ensuring frequently accessed memory blocks reside on shorter paths to the root node. This reduces the verification steps for frequently accessed memory blocks, thereby lowering the overall cost of memory authentication and updates. Experimental results using the USIMM memory simulator demonstrate that compared to the widely used BMT approach, the DCAS-BMT scheme shows a performance improvement of 34.1%. Yu Zhang 0294, Renhai Chen, Hangyu Yan, Hongyue Wu, Zhiyong Feng 0002 |
IEEE Trans. Computers | 1 |