Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging process provides one method to reduce large design margins that are otherwise required to offset circuit aging. This work extends previous research by contributing a sensing scheme that employs on-chip sensors capable of accurately tracking NBTI pMOS current degradations across process, temperature, and varying activity factors. Results show that a 7600$\mu{\hbox {m}}^{2}$sensing area achieves an overall system accuracy of 90% at a voltage threshold precision of 2 mV. We thoroughly describe the sensor design and the underlying statistics used to determine overall accuracy and precision. Furthermore, a novel sensor distribution method is presented that uses an existing scan-chain methodology to mask the overhead of adding the on-chip sensors.

NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks both NBTI and PBTI for both logic and SRAM circuits. Embedded in an SRAM array the sensor takes the form of a 6T SRAM cell and is at least 30x smaller than previous designs. Extensively reusing the SRAM peripheral circuitry minimizes control logic overhead. Sensing overhead is further amortized as the sensors can be both reconfigured and recycled as functional SRAM cells, potentially increasing SRAM yield when other bit cells fail due to initial process variation or long time aging effects. The paper also proposes a variation-aware sensor system design methodology by quantifying and leveraging the tradeoff between the size and number of sensors and the system sensing precision. Design examples show that a system of 500 sensors can achieve 4mV precision with 98.8% confidence, and a system of 1K sensors designed for 1M SRAM bit cells achieves 2000x area overhead reduction compared to a worst-case based approach.

This paper examines the requirements of wearable sensing applications and their implications for designing the next generation of body area sensors. We define key metrics for wearable sensors and discuss how body area sensors differ from generic wireless sensors. To explore the system level issues with a wearable node, we show measurements from a wearable electrocardiogram (ECG) sensor prototype. Using heart rate monitoring as an example, we show how ultra low power (ULP) circuit design must be applied to support the stringent energy and/or power demands of long life wearable sensors. Specifically, sub-threshold operation of digital circuits creates opportunities for re-thinking the entire system. We conclude that we can only reach the lower limits of power consumption through cross-hierarchy design of the entire sensor node that leverages ULP digital circuits.

This paper describes a 130 nm CMOS sub-threshold (sub-VT) mixed-signal system-on-chip (SoC) that acquires and processes an electrocardiogram (ECG) signal for wireless ECG monitoring. Low power ECG devices permit continuous monitoring for longer durations between power recharging. Co-designing the digital and analog blocks creates opportunities for reducing power at the system level. The SoC uses a sub-threshold digital microcontroller (μC) for adaptive control of the sub-VT biased analog components and for processing the ECG data. The μC operates from 0.24 V to 1.2 V and consumes as little as 1.51 pJ per instruction. The SoC consumes only 2.6 μW while providing raw ECG data or processed heart rate data, which can lower the wireless data rate by 500X.

An Automated Unique Tagging System (AUTS) is presented, intended for RFID applications, that generates identification numbers based on random process variations, circumventing the need for non-volatile memories such as EEPROM or Flash. A sense amplifier is used to measure the mismatch in threshold voltage between two identical NMOS devices and generate a 1-bit random output. The AUTS has been fabricated in the TSMC 0.25μm CMOS process and tested.

There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential power analysis (DPA) and simple power analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This paper presents a circuit that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. We discuss the design, simulation results and the limitations of the suppression circuit. We show that this countermeasure significantly increases the number of power trace samples required to undertake a DPA attack. The countermeasure does not require any assumptions about the design of the hardware under protection.

An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell component, a sense amplifier, and two circular shift registers for implementing refresh and read-write pointers. The sense amplifier uses bit-line decoupling to improve readout performance. Our particular application requires the storage of 800 samples of a received ultrasound signal that pass through 48 channels consisting of a preamplifier, a sample-and-hold, and an 8-bit ADC. Data is written into memory in parallel in a sequential, burst-mode fashion and read sequentially at leisure, with interspersed refresh of the memory cells. Layout and design issues concerning implementing memory in a standard 0.25 um process are discussed and simulation results are presented.

A slew rate enhancement technique for operational amplifiers using a tunable active Gm-based current-mode capacitance multiplication circuit instead of the standard Miller compensation capacitor is developed. Low power and low area solutions for driving large capacitive loads are enabled by this technique. In a prototype amplifier, a 0.5 pF MOSFET is multiplied to an effective value of 285 pF, setting the dominant pole at 3 Hz. The slew rate, however, is controlled by the physical MOSFET capacitor. A slew rate as high as 1.5 V/ms is obtained for a standard two stage folded cascode opamp with a 2.5 mA differential pair tail current. An open loop gain of 101 dB and a phase margin of 56° are observed.