Active and Assisted Living (AAL) systems have a purpose to improve the lives of older or impaired people in various aspects. However, the use of equipment for data acquisition in these systems can be considered intrusive in some cases. Although de-identification may provide the needed protection to some extent, it is not always preferred, as it could affect the quality and utility of any obtained data. It is therefore crucial to establish methodologies for protecting the privacy of those monitored and thus affected by AAL systems. The purpose of GoodBrother is to a) analyze any issues arising from the use of monitoring AAL systems, regarding the users' privacy; b) establish proper guidelines for the use of these systems; c) develop privacy-aware methodologies for data handling; d) increase the systems' robustness and reliability; e) create databases to use towards benchmarking. Each one of these objectives are handled by separate interdisciplinary working groups.

In recent years, the Internet of Things (IoT) technology is continuously being applied in the Healthcare domain because of the new services and capabilities it offers. Nevertheless, this technology has many vulnerabilities and network threats that service providers must first overcome before employing IoT-based smart health applications. Specifically, the data privacy, authentication and confidentiality of the system must be ensured because the IoT devices transmit personal health data and the smart health services are directly connected with the users’ wellbeing. Therefore, a complete and secure healthcare architecture based on IoT technology is needed. In this paper, a flexible security and privacy scheme is proposed. The design is based upon the SM4 block cipher and two innovative modes of operation, namely Counter with Cipher Block Chaining-Message Authentication Code (CCM) and Electronic Codebook (ECB), to enhance the flexibility and scalability of the system. The purpose of the architecture is to provide confidentiality to the IoT-based healthcare system and ensure the privacy and authenticity of the data transmitted. The performance results validate the security and hardware efficiency of the novel architecture compared to other related designs. Specifically, the decrease in hardware resources compared to AES-CCM designs is up to 96.7% with the increase in throughput compared to optimized SM4 systems being 71.3%. Overall, the proposed scheme innovatively implements established security primitives while considering the resource limitations and requirements of smart health services.

The major advances in mobile video recording systems have led to an increased number of videos being streamed and uploaded on the internet daily. This has had a major impact on the expansion rate of the IoT with the addition of affordable security systems that capture and stream video content. These systems regularly meet minimal security standards resulting to breaches and data theft. The scientific branch of Computer Forensics has proposed various methods for protecting the confidentiality and integrity of videos, but the need for more robust and effective methods rises as videos grow, in size and number, while compression algorithms are becoming increasingly more efficient. The goal of this paper is to propose a new method on forgery detection, based on the characteristics of Dense Optical Flow. This method is applied on a low-cost device able to capture static CCTV video. The framework is tested for proof of its effectiveness in detecting copy-move, insertion and deletion forgeries. Ultimately, an identification automation method if proposed along with future improvements.

In Digital Forensics science, face detection and recognition techniques are nowadays tightly connected. Investigators need accurate results delivered quickly for their official reports, in order to solve a case. Hardware implementation of face detection and recognition systems have shown to be very efficient with high recognition rate and short processing time. FPGAs are used for such implementations, because of the parallelism and the speed they can offer. In this work, we present the overview and the objectives of the MULTI-FORESEE COST project in this area. We also present alternative face detection FPGA implementations, and present face recognition techniques, for hardware integration. Finally, we compare these implementations with respect to the FPGA resources which are currently used. Efficient and flexible solutions are proposed in relation to computing power, performance, and allocated resources.

Alongside the rapid expansion of Internet of Things (IoT), and network evolution (5G, 6G technologies), comes the need for security of higher level and less hardware demanding modules. New cryptographic systems are developed, in order to satisfy the special needs of security, that have emerged in modern applications. In this paper, a novel lightweight data streaming system, is proposed, which operates in alternative modes. Each one of them, performs efficiently as one of three in total, stream ciphering modules. The operation of the proposed system, is based on reconfigurable logic. It aims at a lower hardware utilization and good performance, at the same time. In addition, in order to have a fair and detailed comparison, a second one design is also integrated and introduced. This one proposes a conventional architecture, consisting of the same three stream ciphering modes, implemented on the same device, as separate operation modules. The FPGA synthesis results prove that the proposed reconfigurable design achieves to minimize the area resources, from 18% to 30%, compared to the conventional one, while maintaining high performance values, for the supported modes.

IoT is a rapidly expanding environment. More and more devices, from the most high-end smartphones, to the most modest environmental sensors, already exhibit or acquire the ability to communicate with each other and be parts of networks. Connectivity is mainly accomplished through wireless communications and privacy is the way to go, regarding security over the air. A common approach dictates the incorporation of a crypto-core inside the transceiver. However, a privacy implementation must take into account several restrictions, imposed by the constrained resources of a small, power efficient device. For this purpose, an incorporation of a hardware implemented lightweight Simeck32/64 block cipher for IEEE 802.15.4 transceiver was proposed. In this work, we examine the FPGA implementation cost of such an approach, and we propose newly designed and efficient implementations of the proposed Simeck32/64 Crypto-Core. Our implementations achieve great improvement in throughput values, with a reasonable increase in hardware area. Furthermore, modifications of these approaches, exploiting the special functional blocks of a Xilinx FPGA, namely BRAM and DSP blocks, are implemented and the achieved results are evaluated. Additionally, the effects of applying the DSP multi-pumping methodology on the aforementioned implementations are also examined.

Nowadays, Internet of Things (IoT) is gradually finding its way, into everybody's life. This paper, introduces both the design and the implementation of a privacy framework, for the Internet of Things (IoT). Taking the benefits from it, a privacy platform is developed with a twofold aim: firstly, to train in detail the fundamentals of cryptography and privacy, and secondly, to make applied cryptography more interactive and flexible. Through this work, the proposed architecture and the integration of this open platform is presented, in detail. In addition, an application of symmetric cryptography is introduced, based on the Advanced Encryption Standard(AES) in various modes of operation, for both encryption and decryption of texts, images and electronic data files.

The whole security architecture of LTE/SAE (Long Term Evolution/System Architecture Evolution) is being consisted of four main hardware-oriented cryptographic algorithms: KASUMI block ciphers, SNOW-3G stream cipher, the MILENAGE algorithm set, and the 4G development of ZUC algorithm. This paper presents an FPGA deployment of a universal security architecture crypto processor for 4G LTE, consisting of both four ciphers enabling each one on demand, which is based on two novel design principles. One is a more intelligent implementation of the four algorithm's substitution boxes (S-boxes) based on a common intersection assumption of their contents. The second includes the use of a common data path hardware block deployed along the four cipher's architectural design. This universal security architecture crypto processor proves to reduce the area space at least 1.5 times, and also provides almost double throughput compared with the state-of-the-art realizations of the individual ciphers, something which is a high necessity when producing components for the demanding post-4G cellular market.

Integrated circuits can be modified with malicious circuitries, like hardware trojans. The use of these circuitries, is either to leak confidential information, or disable security fence of a system, or even to the total destroy of the chip. In this work, several shift registers and a set of logic gates were used to implement key generators. A malicious hardware trojan circuit was added in the combinational circuit, to leak information that were generated. Only a few logical gates are needed to effectively trigger the malicious circuitry, in combination with a flip-flop. These additional gates, have to be included between the shift registers, to be triggered by certain signals, and not to leak in every clock cycle. Taking the advantage of the trigger effect, the malicious circuitry is not delaying the key generators. By implementing the above system, the ability of a hardware trojan to be stealthy under many circumstances, is proven. It is also introduced, from the low demand of logic gates, the little space that is obtained as the effect. It is also proven by the implementation, the very low cost of additional time, which is really needed to perform the leak. Merging those two advantages, the modified circuit that is resulted, is hard to be detected, by a number of applied methods. In particular, in this work a hardware trojan is implemented and added in a stream cipher hardware integration. It is proven, by the implementation results, that the spatial burden is about 2% while the temporal burden is about 3%.

This work targets to the technologies of the Internet of Things (IoT), regarding to security and trusted devices. It provides to the readers a comprehensive understanding of both security and privacy aspects. Modern systems and networks are quoted, in order to cover any questions arising from the theoretical approach. Hardware integration devices are also presented, for flexible implementations for the presented IoT technologies. Emphasis is given to IoT embedded hardware platforms like Udoo, which fully support IoT implementations. Last but not least, data and information preservation are analyzed, so as not to get lost or misused.

In this paper, a methodology towards a hardware/software implementation of an Elliptic Curve Diffie Hellman (ECDH) scheme is proposed in an effort to overcome the design problems of Elliptic Curve Cryptography (ECC) systems stemming from the highly constrained embedded system hardware and software environment (restricted RAM, storage and processing power). To achieve that, instead of the excessively slow software ECDH implementations or monolithic, not flexible hardware implementations, we propose the use of a flexible, scalar multiplication (SM) accelerator connected to the main embedded system processor in order to speed up ECDH functionality without downgrading the overall main processor performance. The proposed solution can be used for a wide variety of GF(2k) based Elliptic Curves (EC) and is capable of shifting from one EC to another EC at runtime (flexibility). The proposed architecture was implemented and tested in Xilinx Virtex 5 technology by realizing the proposed SM accelerator unit interconnected with a Xilinx microblaze softcore processor.

Security is becoming ubiquitous in our society. However, the vulnerability of electronic devices that implement the needed cryptographic primitives has become a major issue. This paper starts by presenting a comprehensive overview of the existing attacks to cryptography implementations. Thereafter, the state-of-the-art on some of the most critical aspects of designing cryptographic co-processors are presented. This analysis starts by considering the design of asymmetrical and symmetrical cryptographic primitives, followed by the discussion on the design and online testing of True Random Number Generation. To conclude, techniques for the detection of Hardware Trojans are also discussed.

Skein is a hash function that reached the semifinals of the NIST competition for the selection of standard SHA-3. This paper describes the implementation of Skein-512 operating as simple hash function and as MAC function. The design was coded using VHDL language and for the hardware implementation, two XILINX FPGAs, Virtex-6 and Virtex-7 were used. The proposed implementation reaches a data throughput of 894 Mbps at 110 MHz clock frequency for Virtex-6 and a throughput of 975 Mbps at 120 MHz clock frequency for Virtex-7.

Keccak hash function has been submitted to SHA-3 competition and it belongs to the final five candidate functions. In this paper FPGA implementations of Keccak function are presented. The designs were coded using HDL language and for the hardware implementation, a XILINX Virtex-5 FPGA was used. Some of the proposed implementations use DSP48E blocks in order to accelerate the designs execution. So, comparisons between the proposed designs in terms of time performance and FPGA resources are given in order to examine the efficiency of the using DSP48E blocks. Also, comparisons with previous published works are provided.

In this paper a hardware implementation of ZUC stream cipher is presented. ZUC is a stream cipher that forms the heart of the 3GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offering reliable security services in Long Term Evolution networks (LTE). A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. The design was coded using VHDL language and for the hardware implementation, a XILINX Virtex-5 FPGA was used. Experimental results in terms of performance and hardware resources are presented.

Hash functions are crucial cryptographic primitives and are widely used in security protocols. Up to now SHA-2 is the proposed NIST standard for hash functions, but is going to be substituted by the end of the next year. NIST is holding up a public competition to select a new hash algorithm(s), called SHA-3 (Secure Hash Algorithm Version 3), for the purpose of completely superseding the functions of the SHA-2 family. The four finalists have been selected by NIST, and a year is allocated for the public review of these algorithms. BLAKE hash functions family is one of the most promising finalists. A multi-module hashing system for this hash functions family, and the FPGA integration of it, are proposed in this work. The introduced system supports a multi-module operation in the sense that upon to the users selection performs efficiently for all hash functions of BLAKE family: -28, -32, -48, -64. The proposed multi-module system is compared with the stand alone implementations of each of the hash functions, integrated in separate FPGA devices. Comparisons with previously published related works are also presented, in order to have a fair and detailed evaluation of the proposed design methodology. Compared with them, the proposed multi-module system performs with higher operation frequency and allocates less silicon area resources. Finally, the proposed performs better, compared with other ones, in the term of throughput on a range of 100% to 500% and better at about 50%, compared with area-delay product factor.

Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Two major gate level techniques are introduced in order to reduce the power consumption, namely the pipeline technique (with some variants) and the use of embedded RAM blocks instead of general purpose logic elements. Power consumption reduction from 1.2 to 8.7 times is achieved by means of the proposed techniques compared with the implementation without any low power issue.

Compact and high-speed hardware architectures for the 192-bit hash function Tiger are proposed and their gate counts and throughputs are evaluated using a 90-nm CMOS standard cell library. The implementations achieve practical performances of 22.5 K with 2.2 Gbps and 46.4 Kgates with 6.95 Gbps. These throughputs are 1.5-2 times higher than those of the SHA hash family SHA-256/-512, but the hardware efficiencies (defined as throughput per gate) of Tiger are lower than those of SHA and are half those of the Whirlpool hash function. Hardware performance is one of the most important features for hash functions to be selected as a next standard algorithm after SHA. Therefore, the requirements for hash functions to achieve flexible and high-performance circuits are also clarified through this study by analyzing the characteristics of structure and basic components of each algorithm from the viewpoint of hardware implementation.

Abstract Universal mobile telecommunication system (UMTS) has specified security mechanisms with extra features compared to the security mechanisms of previous mobile communication systems (GSM, DECT). A hardware implementation of the UMTS security mechanism is presented in this paper. The proposed VLSI system supports the Authentication and Key Agreement procedure (AKA), the data confidentiality procedure, and the integrity protection procedure. The AKA procedure is based on RIJNDAEL Block Cipher. An efficient RIJNDAEL architecture is proposed in order to minimize the usage of hardware resources. The proposed implementation performs the AKA procedure within 76 µs comparing with the 500 ms that UMTS specifies. The data confidentiality and the integrity protection is based on KASUMI Block Cipher. The proposed KASUMI architecture reduces the hardware resources and power consumption. It uses feedback logic and positive‐negative edge‐triggered pipeline in order to make the critical path shorter, without increasing the execution latency. The S‐BOXes that are used from RIJNDAEL and KASUMI block ciphers have been implemented with combinational logic as well as with ROM blocks. Copyright © 2006 John Wiley & Sons, Ltd.

Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications with low covered area resources. The second architecture is optimized for high-speed performance using pipelined technique. Its throughput can reach 3.65 Gbit/sec.