EDBT 2026 Demo / reviewers in the wild / expert
Waldemar Horwat
dblp:50/99
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Programming languages and type systems · 44% Services computing and microservices · 44% Compilers and program optimization · 13% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 56% Processor architecture and microarchitecture · 44% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Programming languages and type systems
concurrent programming languages |
0.0 | 1 | 1989 | Experience with CST: Programming and Implementation · PLDI 1989 |
Services computing and microservices › middleware
distributed objects |
0.0 | 1 | 1989 | Experience with CST: Programming and Implementation · PLDI 1989 |
Processor architecture and microarchitecture › multithreading
context switching |
0.0 | 1 | 1987 | Architecture of a Message-Driven Processor · ISCA 1987 |
Parallel and multicore computing › parallel architecture
message-passing architecture |
0.0 | 1 | 1987 | Architecture of a Message-Driven Processor · ISCA 1987 |
Compilers and program optimization › code generation
native code generation |
0.0 | 1 | 1989 | Experience with CST: Programming and Implementation · PLDI 1989 |
Methods — techniques the papers use, named apart from their topics
compiler optimization · 0.0simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | The Message Driven Processor: An Integrated Multicomputer Processing ElementabstractA description is given of the Message-Driven Processor (MDP), an integrated multicomputer node. It incorporates a 36-bit integer processor, a memory management unit, a router for a 3D mesh network, a network interface, a 4K*36-bit word static RAM (SRAM), and an ECC dynamic RAM (DRAM) controller on a single 1.1 M-transistor VLSI chip. The MDP is not specialized for a single model of computation. Instead, it incorporates efficient primitive mechanisms for communication, synchronization, and naming. These mechanisms support most proposed parallel programming models. Each processing node of the MIT J-Machine consists of an MDP with 1 Mbit of DRAM.> William J. Dally, Andrew A. Chien, Stuart Fiske, Gregory A. Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills |
ICCD | 5 |
| 1989 | Experience with CST: Programming and ImplementationabstractCST is a programming language based on Smalltalk-802 that supports concurrency using locks, asynchronous messages, and distributed objects. In this paper, we describe CST: the language and its implementation. Example programs and initial programming experience with CST are described. Our implementation of CST generates native code for the J-machine, a fine-grained concurrent computer. Some compiler optimizations developed in conjunction with that implementation are also described. Waldemar Horwat, Andrew A. Chien, William J. Dally |
PLDI | 1 |
| 1987 | Architecture of a Message-Driven ProcessorabstractWe propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Brian Totty, D. Scott Wills |
ISCA | 5 |