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Youngsub Ko

dblp:51/10811 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 67% GPUs and heterogeneous computing · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing › CPU-GPU heterogeneous computing
CPU-GPU heterogeneous platforms
0.212014
Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms · DAC 2014
Performance modeling and evaluation › simulation › architectural simulation
full-system simulation
0.212014
Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms · DAC 2014
Performance modeling and evaluation
simulation
0.212014
Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms · DAC 2014

Methods — techniques the papers use, named apart from their topics

hardware-in-the-loop simulation · 0.2gem5 · 0.2
YearPublicationVenuePosition
2015 Fast GPU-in-the-loop simulation technique at OpenGL ES API level for Android Graphics Applications
abstract
Building a full system simulator for a CPU-GPU heterogeneous architecture recently draws keen attention of mobile device developers who want to run full software stacks without modification. A common practice is to integrate a GPU simulator with a CPU simulator, which runs very slow or is not applicable when the GPU simulator does not exist. To overcome these drawbacks, a HIL (Hardware-in-the Loop) simulation approach that integrates a real GPU with a CPU simulator has been proposed recently, in which HIL simulation is performed at the device driver level, supporting a specific GPU only. For design space exploration of CPU-GPU heterogeneous architecture, it is necessary to support various GPUs. To this end, we propose a GPU-HIL simulation technique that integrates a real GPU at the OpenGL ES API level, aiming to make a good compromise between speed and timing accuracy. Technical challenges and proposed solutions are presented in detail. Using three OpenGL ES Android benchmarks, preliminary experiments show some use cases of the proposed simulation framework for design space exploration and API-level dynamic behavior monitoring.
Youngsub Ko, Youngmin Yi, Joongbaik Kim, Soonhoi Ha
RSP1
2014 Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms
abstract
Multi-core CPU/GPU heterogeneous platforms became popular in embedded systems. A full system simulator is typically used to observe the internal system behavior by running complete software stacks without modification on simulation models of CPUs and other devices in the system. However, there are few known full system simulators for CPU/GPU heterogeneous platforms and existent GPU simulators are prohibitively slow for running application software. In this paper, we propose a hardware-in-the-loop simulation technique that integrates GPU hardware into a full system simulator. A novel interfacing mechanism between CPU simulator and the development board, where GPU hardware is integrated, is devised. In the experiments, we took Exynos 4412 as a case study, where gem5 simulator is used to simulate mainly a quad-core ARM CPU in the platform and an Exynos development board is used to run the Mali GPU hardware. We could successfully run Android apps on the proposed hardware-in-the-loop simulation framework with up to 1.5 M cycles per second performance.
Youngsub Ko, Youngmin Yi, Myungsun Kim, Soonhoi Ha
DAC1