In this article, we study the problem of how to maximize the throughput of a periodic real-time system under a given peak temperature constraint. We assume that different tasks in our system may have different power and thermal characteristics. Two scheduling approaches are presented. The first is built upon processors that can be in either active or sleep mode. By judiciously selecting tasks with different thermal characteristics as well as alternating the processor's active / sleep mode, the sleep period required to cool down the processor is kept at a minimum level, and, as the result, the throughput is maximized. We further extend this approach for processors with dynamic voltage/frequency scaling (DVFS) capability. Our experiments on a large number of synthetic test cases as well as real benchmark programs show that the proposed methods not only consistently outperform the existing approaches in terms of throughput maximization, but also significantly improve the feasibility of tasks when a more stringent temperature constraint is imposed.

We study the problem on how to maximize the throughput for a periodic real-time system under the given peak temperature constraint. We assume that different tasks in our system may have different power and thermal characteristics. Two algorithms are presented in this paper. The first one is built upon processors that can be either in active or sleep mode. By judiciously selecting tasks with different thermal characteristics as well as alternating the processor active/sleep mode, our approach can improve the throughput upon the existing techniques by 21% in average. We further extend this approach for processors with dynamic voltage/frequency scaling (DVFS) capability. Our experiments show that an improvement of 24% can be achieved when compared with the existing methods.

In this paper, we propose a novel method for analyzing fewer hot spots in a chip. The method, called SNSOR (Single-Node Successive Over Relaxation), is based on a novel localized relaxed iterative approach to perform statistical analysis on one hot spot at a time. Based on SNSOR, we propose an approximation method, called ET-SNSOR (Electro-Thermal SNSOR), to deal with the electro-thermal coupling (ETC) effects. ET-SNSOR first uses the iterative method to update correlations from ETC, and then computes standard temperature deviations for hot spots, according to ETC and updated correlations. Experiments show that ET-SNSOR is three orders of magnitude faster than the Monte-Carlo method with small errors (less than 4.76% on maximum). It only takes an average of 0.18 second to analyze one hot spot statistically for a large test case of 1.3M nodes with ETC effects.

Ensemble-classifier is a technique that uses a combination of multiple classifiers to reach a more precise inference result than a single classifier. In this paper, a three-layer hierarchy multi-classifier intrusion detection architecture is proposed to promote the overall detection accuracy. For making every individual classifier is independent from others, each uses a diverse soft computing technique as well as different feature subset. In addition, the performances of a variety of combination methods that fuse the outputs from classifiers are studied. In the experiments, DARPA KDD99 intrusion detection data set is chosen as the evaluation tools. The results show that our approach achieves a better performance than that of a single classifier.

This paper presents a method of integration and implementation of transmitting video and audio data from multiple Internet protocol (IP) surveillance cameras in a wireless sensor network to a centralized management unit (central node) using real time streaming protocol (RTSP). The wireless network is based on ldquostarrdquo topology by using the IEEE 802.11 series of standards in wireless local area networks (WLAN). Security for wireless communications between the sensors and central node is achieved in real-time through the proposed uncertainty classification of network traffic with little and negligible run-time overhead for hacker or threat detection. A correlation-based feature selection algorithm is utilized in the central node for improved intrusion detection speed and accuracy by eliminating redundant and irrelevant features in the feature space. Uncertainty problems are solved using the fuzzy belief k-nearest neighbours (k-NN) intrusion detector, which incorporates the fuzzy clustering technique with the Dempster-Shafer theory. Also, the detection process is made more efficient using the k-NN technique. Experimental results show up to 94% detection rate of potential threats and intrusions, which indicate a significant performance increase compared with three other classifiers.

In this paper, we have proposed a thermal aware routing based parameterization to generate a clock model that takes the stochastic temperature variation into consideration. The worst-case skew is calculated by using the transient analysis. The proposed Thermal Aware Routing based Clock Tree Optimization (TARCO) is performed level by level via the use of sensitivities from the proposed macromodel. The experimental results show that our algorithm reduces up to 5X worst-case skew in comparison to the existing bonded-skew based Deferred Merge Embedding (DME) approach, and 1.7X worst-case skew compared to Perturbation based Clock Optimization (PECO) and 2.1X compared to Temperature Aware Clocktree Optimization (TACO).

In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sources. The new method inserts decoupling capacitors (decaps) into the power grid networks to reduce the voltage fluctuation. The optimization is based on sensitivity-based conjugate gradientmethod and sequence of linear programming approach. Different from existing power grid noise reduction methods, the new approach considers the impacts of inter-die and intra-die variational leakage current sources due to unavoidable process variability during the decap optimization process for the first time. Leakage currents, which although are static in nature typically, can still add to the total voltage drops and dynamic voltage reduction thus must consider the leakage-induced voltage variations. The proposed algorithm exploits the relative constant variations for different decap configurations of power grid circuits to speed up the statistical optimization process. Decaps can be inserted in such a way that the resulting circuits have much higher probability to meet the voltage drop constraints in the presence of leakage current variations. Experimental results demonstrate the effectiveness of the proposed approach and show that the new method has 100X to 1,000X of speedup over the Monte Carlo based statistical decap optimization method.

In this paper, we present a novel pattern-based method to simulate large-scaled power/ground (P/G) grids. This method takes advantage of both traditional direct simulation methods and iterative simulation methods. The new method explores the geometry characteristics of regular P/G grids and translates topology similarity to submatrix regularity, which is called “pattern” in this paper. Such pattern structures can reduce the memory usage dramatically. Further, a new type of preconditioner is constructed to optimize the simulation process. Experimental results show that the proposed approach is about 5$\times$faster than the previous iterative methods with much lower memory, and is superior to the macro model-based hierarchical method on the tested large cases with pattern structures.

As the technology scales into 90 nm and below, process-induced variations become more pronounced. In this paper, we propose an efficient stochastic method for analyzing the voltage drop variations of on-chip power grid networks, considering log-normal leakage current variations with spatial correlation. The new analysis is based on the Hermite polynomial chaos (PC) representation of random processes. Different from the existing Hermite PC based method for power grid analysis, which models all the random variations as Gaussian processes without considering spatial correlation. The new method focuses on the impacts of stochastic sub-threshold leakage currents, which are modeled as log-normal distribution random variables, on the power grid voltage variations. To consider the spatial correlation, we apply orthogonal decomposition to map the correlated random variables into independent variables. Our experiment results show that the new method is more accurate than the Gaussian-only Hermite PC method using the Taylor expansion method for analyzing leakage current variations, and two orders of magnitude faster than the Monte Carlo method with small variance errors. We also show that the spatial correlation may lead to large errors if not being considered in the statistical analysis.

This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today's very large scale integration physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But several new techniques that significantly improve the efficiency of the optimization process were adopted. First, an efficient search step scheme to replace the time-consuming line search phase in the conventional CG method for decap budget optimization was proposed. Second, instead of optimizing an entire large circuit, the circuit is partitioned into a number of smaller subcircuits and optimized separately by exploiting the locality of adding decaps. Third, the time-domain merged adjoint method was applied to compute the sensitivity information and show that the partitioning-based merged adjoint method leads to better results than the flat merged adjoint method with the improved search scheme. Experimental results show that the proposed algorithm achieves at least ten times speed-up over similar decap allocation methods reported so far with similar budget quality, and a power grid circuit with about one million nodes can be optimized using the new method in half an hour on the latest Linux workstations