Demo Data from EDBT 2026 / reviewers in the wild / expert
Philip Bitar
dblp:51/1428
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 56% Memory systems · 44% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache coherence |
0.0 | 1 | 1986 | Multiprocessor Cache Synchronization: Issues, Innovations, Evolution · ISCA 1986 |
Parallel and multicore computing
synchronization |
0.0 | 1 | 1986 | Multiprocessor Cache Synchronization: Issues, Innovations, Evolution · ISCA 1986 |
Parallel and multicore computing › synchronization
read-modify-write |
0.0 | 1 | 1986 | Multiprocessor Cache Synchronization: Issues, Innovations, Evolution · ISCA 1986 |
Methods — techniques the papers use, named apart from their topics
protocol design and analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | The Weakest Memory-Access Order
Philip Bitar |
J. Parallel Distributed Comput. | 1 |
| 1986 | Multiprocessor Cache Synchronization: Issues, Innovations, EvolutionabstractMany options are possible in a cache synchronization (or consistency) scheme for a broadcast system. We clarify basic concepts, analyze the handling of shared data, and then describe a protocol that we are currently exploring. Finally, we analyze the evolution of options that have been proposed under write-in (or write-back) policy. We show how our protocol extends this evolution with new methods for efficient busy-wait locking, waiting, and unlocking. The lock scheme allows locking and unlocking to occur in zero time, eliminating the need for test-and-set. The scheme also integrates processor atomic read-modify-write instructions and programmer/compiler busy-wait-synchronized operations under the same mechanism. The wait scheme eliminates all unsuccessful retries from the bus, and allows a process to work while waiting. Philip Bitar, Alvin M. Despain |
ISCA | 1 |