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Jie-Yong Juang

dblp:51/1680 · DBLP profile ↗
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18ranked-venue papers
6as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 11 · 4 first-authorSoftware engineering, systems software and programming languages · 3Applied, interdisciplinary, general and emerging computing · 3Artificial intelligence and machine learning · 2Computer networks · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Interconnection networks and networks-on-chip · 63% Parallel and multicore computing · 13% Distributed systems · 11%
Computer networks
2 papers
Wireless networking · 66% Transport protocols and congestion control · 25% Internet architecture and protocols · 9%

Topics — the 11 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › arbitration
bus arbitration
0.011991
A Contention-Based Bus-Control Scheme for Multiprocessor Systems · IEEE Trans. Computers 1991
Interconnection networks and networks-on-chip › switching network
circuit-switched network
0.011989
Resource Sharing Interconnection Networks in Multiprocessors · IEEE Trans. Computers 1989
Parallel and multicore computing
multiprocessor system
0.021991
A Contention-Based Bus-Control Scheme for Multiprocessor Systems · IEEE Trans. Computers 1991
Resource Sharing Interconnection Networks in Multiprocessors · IEEE Trans. Computers 1989
Distributed systems › distributed resource management
distributed resource scheduling
0.011985
Resource Scheduling for Local Computer Systems with a Multiaccess Network · IEEE Trans. Computers 1985
Wireless networking
collision resolution
0.011984
Unified Window Protocols for Contention Resolution in Local Multi-Access Networks · INFOCOM 1984
Wireless networking
medium access control
0.011984
Unified Window Protocols for Contention Resolution in Local Multi-Access Networks · INFOCOM 1984
Transport protocols and congestion control
window protocol
0.011984
Unified Window Protocols for Contention Resolution in Local Multi-Access Networks · INFOCOM 1984
Electronic design automation › high-level synthesis › scheduling
processor scheduling
0.011991
A Contention-Based Bus-Control Scheme for Multiprocessor Systems · IEEE Trans. Computers 1991
Cloud and datacenter computing › cluster resource management and scheduling
resource scheduling
0.011989
Resource Sharing Interconnection Networks in Multiprocessors · IEEE Trans. Computers 1989
Internet architecture and protocols
local area network
0.011985
Resource Scheduling for Local Computer Systems with a Multiaccess Network · IEEE Trans. Computers 1985
Wireless networking
multiaccess network
0.011985
Resource Scheduling for Local Computer Systems with a Multiaccess Network · IEEE Trans. Computers 1985

Methods — techniques the papers use, named apart from their topics

collision detection · 0.0splitting algorithms · 0.0token propagation · 0.0network flow algorithm · 0.0extremum identification · 0.0broadcast protocols · 0.0
YearPublicationVenuePosition
1995 Design and implementation of a multicomputer interconnection network using FPGAs
abstract
We present an experience of using FPGAs in the design and implementation of a multicomputer interconnection network. The switching element, the router and the network controllers are all designed and implemented with FPGAs, and cooperatively form a four port by four port interconnection network. The switching elements were designed with ASIC before, but were not very successful. Advantages of using FPGAs over traditional ASIC design are discussed.
Chun-Chao Yeh, Chun-Hsing Wu, Jie-Yong Juang
FCCM3
1994 Are We Providing the Right Education for Computer Science/Engineering Students?
Jesse Fang, Yarsun Hsu, Shing-Tsaan Huang, Jie-Yong Juang, W. H. Tsai, Horst F. Wedde
ICPADS4
1993 A Method for Translating CLP (R) Rules into Objects
abstract
A method translating CLP(R) rules into object classes of OOP is presented. Operationally, the original inference process is replaced by simple object invocation. Backtracking is accomplished by a while loop in a class member function. Mathematical constraints are collected incrementally when corresponding constraint objects are invoked. In this manner, mathematical models composed of such constraints can also be formed dynamically along the way of object invocation. During execution, objects of are created and the communications among them are through the message passing scheme. After the translation, there is no distinctions between rules and ordinary procedural functions because they are all the same in the form of classes. Therefore, powerful and efficient computational procedures, such as mathematical solvers, can be easily integrated with the original reasoning process so that traditional logic programs which are intelligent but less efficient can be equipped with powerful procedures to upgrade efficiency. Moreover, because of the rich resources on the OOP platform nowadays, the translation process also greatly increases the flexibility and portability of a CLP(R) system.
Ta-Cheng Yu, Jie-Yong Juang
ICTAI2
1993 Concurrent Query Processing for Logic Inference Using the Connection Graph
Naim Abdullah, Jie-Yong Juang
J. Parallel Distributed Comput.2
1991 Information caching in the execution of logic programs
abstract
A model is proposed that integrates information caching into inference procedure. In addition to success results, failure information is also cached in this model to facilitate back-tracking. A logic system based on this model was implemented. Results of running a set of representative logic programs on the system are reported.>
Chih-Hao Huang, Jie-Yong Juang
COMPSAC2
1991 3-D structure modeling via constraint resolution
abstract
A study is made of the design of a tool for developing structure modeling systems. A constraint logic programming scheme is the framework chosen for the system. In order to determine the structure of a set of objects by resolving geometric relations, the representation scheme, which is based on rigid transformations, is used to express geometric relations algebraically. Parameters not determined in a relation formula may be determined by correlating them with other formulae. This is done automatically by constraint resolution.>
Hsiao-Rong Tyan, Jie-Yong Juang
ICTAI2
1991 A Contention-Based Bus-Control Scheme for Multiprocessor Systems
abstract
The authors study contention-based bus-control schemes for scheduling processors in using a bit-parallel shared bus. The protocol is designed under the requirements that each processor exhibit a random access behavior, that there be no centralized bus control in the system, and that access be granted in real time. The proposed scheme is based on splitting algorithms used in conventional contention-resolution schemes, and utilizes two-state information obtained from collision detection. Two versions of the bus-control scheme are studied. The static one resolves contentions of N requesting processors in an average of O(log/sub W/2/N) iterations, where W is the number of bits in the bit-parallel bus. An adaptive version resolves contentions in an average time that is independent of N.>
Jie-Yong Juang, Benjamin W. Wah
IEEE Trans. Computers1
1990 A Partial Compaction Scheme for Processor Allocation in Hypercube Multiprocessors
Chih-Hao Huang, Jie-Yong Juang
ICPP (1)2
1989 On processor allocation in hypercube multiprocessors
abstract
The processor allocation problem in a hypercube system is to find a free subcube for a given request. The subcube recognition capability of existing allocation strategies, e.g. the buddy strategy and the Gray code strategy, is far below the theoretical upper bound due to their incomplete representation of the hypercube interconnection structure. A complete strategy that outperforms the existing ones in subcube recognition capability and average waiting time but incurs a higher overhead is proposed. Efficient implementation of the complete strategy is also studied.>
Chih-Hao Huang, Ting-Lu Huang, Jie-Yong Juang
COMPSAC3
1989 Application of mathematical constraint resolution to decision support system
abstract
It is shown how a mathematical constraint resolution (MATHCORE) system can be used to design a better decision support system. MATHCORE not only has the flexibility of expressing mathematical equations within a logic programming paradigm in a natural way, but also has an ability to deal with systems of nonlinear equations, regression analysis, and optimization problems. While most existing constraint logic programming systems try to devise their own constraint solvers and are confined to systems of linear equations and simple nonlinear functions, the MATHCORE removes this limitation by directly taking advantage of well-developed numerical methods available in the mathematical libraries. With MATHCORE, complex decision optimization models can be embedded in a rule-based decision support system. Using this methodology, it is demonstrated that the interactions among various economic factors in a housing market can be stated in the program body, while various (optimization) goals of social welfare can be expressed as queries.>
Feng-Tyan Lin, Jie-Yong Juang, D. T. Lee
COMPSAC2
1989 Message Flow Analysis and Run-Time Verification for Parallel Programs
Sheausong Yang, Jie-Yong Juang
ICPP (2)2
1989 A unified minimum-search method for resolving contentions in multiaccess networks with ternary feedback
Jie-Yong Juang, Benjamin W. Wah
Inf. Sci.1
1989 Load Balancing and Ordered Selections in a Computer System with Multiple Contention Buses
Jie-Yong Juang, Benjamin W. Wah
J. Parallel Distributed Comput.1
1989 Resource Sharing Interconnection Networks in Multiprocessors
abstract
Circuit-switched interconnection networks for resource sharing in multiprocessors are studied. Resource scheduling in systems with such an interconnection network entails the efficient search for a mapping from requesting processors to free resources such that circuit blockages in the network are minimized and resources are maximally used. The optimal mapping is obtained by transforming the scheduling problems into various network flow problems to which existing algorithms can be applied. A distributed architecture to realize a maximum flow algorithm using token propagations is described. The method is applicable to any general loop-free network configuration in which the requesting processors and free resources can be partitioned into two disjoint subsets.>
Jie-Yong Juang, Benjamin W. Wah
IEEE Trans. Computers1
1988 Parallelism in Connection-Graph-Based Logic Inference
Jie-Yong Juang, Ting-Lu Huang, Ed Freeman
ICPP (2)1
1986 Resource Sharing Interconnection Networks in Multiprocessors
Benjamin W. Wah, Jie-Yong Juang
ICPP2
1985 Resource Scheduling for Local Computer Systems with a Multiaccess Network
abstract
A study of resource scheduling based on a distributed state-dependent discipline for a system of processors connected by a local multiaccess network is made. The scheduling problem is reduced to the identification of the extremum from a set of physically dispersed random numbers. The authors propose an efficient method of utilizing the primitive operations of collision detection and broadcast in multiaccess networks to efficiently distribute status information and to identify the extremum. The optimal performance of extremum identification is found to be constant and on the average independent of the number of contending processors. The protocol can be implemented either by minor hardware modification of existing multiaccess-network interfaces or in software.
Benjamin W. Wah, Jie-Yong Juang
IEEE Trans. Computers2
1984 Unified Window Protocols for Contention Resolution in Local Multi-Access Networks
Jie-Yong Juang, Benjamin W. Wah
INFOCOM1