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Andrew Lines

dblp:51/2085 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
asynchronous circuit design		 0.212014
Performance-Driven Clustering of Asynchronous Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Electronic design automation › high-level synthesis › pipeline synthesis
automatic pipelining		 0.212014
Performance-Driven Clustering of Asynchronous Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Electronic design automation
high-level synthesis		 0.212014
Performance-Driven Clustering of Asynchronous Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014

Methods — techniques the papers use, named apart from their topics

clustering algorithm · 0.2
YearPublicationVenuePosition
2014 Performance-Driven Clustering of Asynchronous Circuits
abstract
This paper proposes the method of generating asynchronous circuits from hardware description language specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput and latency constraints, and minimizing area. This method provides a form of automatic pipelining in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original Register-Transfer Level (RTL) specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles.
Georgios D. Dimou, Peter A. Beerel, Andrew Lines
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3