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Hidenori Umeno

dblp:51/2350 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Operating systems · 67% Runtime systems and virtual machines · 33%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Cloud and datacenter computing · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Runtime systems and virtual machines › interpreter
direct execution
0.011987
New Methods for Realizing Plural Near-Native Performance Virtual Machines · IEEE Trans. Computers 1987
Operating systems › virtualization
i/o virtualization
0.011987
New Methods for Realizing Plural Near-Native Performance Virtual Machines · IEEE Trans. Computers 1987
Operating systems
virtualization
0.011987
New Methods for Realizing Plural Near-Native Performance Virtual Machines · IEEE Trans. Computers 1987
Cloud and datacenter computing
virtualization
0.011987
New Methods for Realizing Plural Near-Native Performance Virtual Machines · IEEE Trans. Computers 1987

Methods — techniques the papers use, named apart from their topics

address translation · 0.0
YearPublicationVenuePosition
2005 New Method for Dispatching Waiting Logical Processors in Virtual Machine Systems
abstract
A virtual machine system can run multiple conventional operating systems (OSs) in a single real host computer. A virtual machine is a logical computer with almost the same architecture as the host, and may contain several logical processors. A hypervisor is a control program to control this virtual machine system. Traditionally, the hypervisor has to receive an I/O interrupt pending for a waiting logical processor, and to simulate the I/O interrupt, consequently incurring the simulation overhead of the I/O interrupt. To avoid this overhead we present a new method which introduces a new self-wait state different from the conventional wait state, presents a new instruction for the hypervisor to detect the I/O interrupts pending for the logical processors in the self-wait state, and dispatches those logical processors on the detection ahead of the ready queue. This new method has eliminated the simulation overhead of those I/O interrupts, and enhanced the system performance to the near native.
Hidenori Umeno, Masato Kiyama, Takafumi Fukunaga, Takashige Kubo
COMPSAC (1)1
1987 New Methods for Realizing Plural Near-Native Performance Virtual Machines
abstract
This paper presents methods for increasing the efficiency of operating systems in plural virtual machines to a near-native performance level. The proposed direct execution methods support direct I/O execution for plural virtual machines, that is, the V = R virtual machine, and the V = Resi virtual machines, including both I/O instruction issuances and I/O interrupts. All V = Resi virtual machines have an entirely resident memory and their real addresses are translated into those of the host simply by adding a constant, α(≠ 0), which constitutes a starting address given to each V = Resi virtual machine. The V = R virtual machine has almost the same memory attribute as the V = Resi VM except for α = 0. Only one V = R virtual machine can be present in all virtual machines. The experimental results obtained confirm that a near-native performance level, that is, a level exceeding 90 percent of native performance, can be realized for the V = R virtual machine as well as for the V = Resi virtual machines.
Hidenori Umeno, Shunji Tanaka
IEEE Trans. Computers1