This paper presents a 2.4 GHz RF energy-harvesting CMOS chip with a co-designed dipole antenna, implemented in a standard 180 nm CMOS process and occupying an area of 2.56$\times $2.68 mm2. The proposed design includes a reconfigurable rectifier, a maximum power harvesting efficiency optimization (MPHEO) controller, a$3\times $switched-capacitor charge pump (SCCP$3\times $), an ultra-low-power diode (ULPD), and several key analog building blocks. A discrete$\pi $-matching network and dipole antenna are fabricated on an FR-4 substrate and a flexible polyimide printed circuit board, respectively. Measurement results demonstrate a peak RF front-end power harvesting efficiency (PHE) of 55.1% at −1 dBm input and a sensitivity of −16.2 dBm at 1.1-V output voltage. The SCCP$3\times $achieves a peak power conversion efficiency of 97.4%, while the ULPD exhibits sub-2 nA reverse leakage. The MPHEO algorithm extends the >20% PHE range across a 25 dB input power span from −12.2 dBm to 12.8 dBm, confirming the system’s high efficiency, robustness, and adaptability for low-power wireless energy harvesting applications.

This paper presents a class-C cross-coupled differential CMOS rectifier with an active modulation technique enabled by dual-path feedback loops. The proposed design effectively mitigates reverse leakage current losses at high input power levels, thereby enhancing power conversion efficiency (PCE) and extending the input power range (IPR). Unlike conventional designs that employ resistive or diode-based feedback control circuits in the DC path, leading to degraded PCE at high RF power levels and additional power consumption in the feedback loop, the proposed scheme incorporates a fully active modulation mechanism that improves PCE across a wide frequency range. Fabricated in a standard 180 nm CMOS process, the rectifier occupies a compact active area of 0.009 mm$\mathbf {^{2}}$. Measured at a 100 k$\boldsymbol {\Omega }$load, the design achieves a peak PCE greater than 76%, an IPR (PCE >60%) spanning over 8.8 dB, and a sensitivity better than -18 dBm for generating a 1 V output consistently at 433 MHz, 920 MHz, and 2.4 GHz operating frequencies.

This paper presents a sub-1V output voltage reference circuit using a 0.18-μm CMOS technology. The circuit uses a stacked-diode-MOS-transistor (SDMT) architecture, which ensures excellent supply and temperature independence at low power consumption. Additionally, leakage-based temperature compensation allows for an expanded operating temperature range, while frequency compensation techniques extend the bandwidth of supply rejection. The design achieves a temperature coefficient of 34.6 ppm/°C over a range of -50 to 130 °C, a line sensitivity of 0.014 %/V, and a power supply rejection ratio of -67 dB at 100 Hz. The circuit consumes only 600 pW of power and takes up a chip area of 0.0079 mm2.

This paper presents an energy-efficient resistor-to-digital converter (RDC) to detect a wide resistance range force sensing resistor (FSR). The proposed RDC leverages a delta-sigma architecture, enabling a high linear readout range while maintaining excellent power efficiency. The design was fabricated in a 0.18-μm CMOS process. The SNDR of the design achieves 75.3 dB with a rapid measurement time of 0.17 ms while consuming only 42.78 μW. The energy efficiency figure of merit (FoM) is 1.54 pJ per measurement, and the architecture maintains 0.999 R2linearity in the resistance measurement range from 6.8 kΩ to 2.2 MΩ. The chip area is 2 mm2.

This paper presents a capacitive sensor readout IC with low power consumption and an extensive linear range. The proposed capacitance readout circuitry adopts capacitor-to-frequency (C2F) architecture to suppress the effect of amplitude noise by converting the analog signal to frequency. Then, the inverter-based time-to-digital converter (DTDC) digitalizes the frequency information. A feedback loop with a switchable capacitive bank to lock the C2F input capacitance and adjustable conversion rate are employed to enhance the linear capacitance detection range. The pulse width in a period represents the detected capacitance information. The design was fabricated in a 0.18 μm CMOS process, and the chip area is 1.38 mm2. The proposed design achieves linearities of 0.9999, 0.9999, and 0.9965, whereas the sensitivity is adjusted to 5.6, 14.9, and 2 μs/pF, respectively. The Allen deviation floor of C2F is 0.97 Hz, and the sensing capacitance range is 20-90 pF while only consuming 31 μW.

This paper presents an electrochemical sensing chip with an integrated current-reducer pattern generator and a low-noise chopper-stabilization potentiostat circuit. The pattern generator, utilizing the current reducer technique and pseudo resistors, creates a sub-Hz ramp signal for the cyclic voltammetric measurement without large-size passive components. The proposed design adopts a chopper-stabilization potentiostat and time-based converter to reduce the amplitude noise effects. The design is fabricated using a 0.18-μm CMOS process and achieves a 41pA current resolution in the current range of ± 5μA while maintaining the R2linearity of 0.998. The power consumption of the design is 16μW when a 5μA sensing current is detected. The power efficiency of the readout interface is 0.31 and the sensing current dynamic range is 108dB. The design is fully integrated into a single chip.

For wide-range deployment of wireless sensing nodes in power and size-constrained Internet of Things applications, self-sustaining wireless sensors without batteries are needed. The energy supply for these ubiquitous sensing devices should harness environmental energy sources to avoid frequent battery replacement and pollution. This paper presents a new soil energy harvesting system with a power management integrated circuit (IC) for wide-range maximum power point tracking (MPPT). The output power of a soil energy cell varies widely according to the soil moisture and soil contents. To extract the maximum amount of energy from the soil, high-efficiency power management with adaptive dc-dc conversion ratios and an MPPT mechanism is essential. The proposed system is implemented with a high-efficiency dc-dc converter IC in a 0.18-μm CMOS process. The design achieves a peak tracking efficiency of 90.5% in the throughput power range from 56 μW to 1 mW at an output voltage of 3 V and system efficiency exceeding 65% over an input resistance range of the soil energy source; the peak system efficiency is 73.9%. A demonstration was undertaken of the soil energy harvesting system lighting an LED array without any chemical batteries.

This paper presents a low-power electrochemical sensor readout IC with a bi-directional potentiostat for accommodating a large dynamic sensing current range. The proposed chopper stabilization potentiostat, suppressing low-frequency noise at the front end and providing stable positive and negative potentials between the working and reference electrodes for bi-directional current sensing through a switched push-pull readout stage. The digital implementation of an oscillator-based current to frequency converter and frequency counter transforms the sensing current directly into digital codes. The design is realized in a 0.18μm CMOS process and occupies an area of 1.3mm2, including all passive components and pads. The proposed readout IC achieves a 0.9pA minimum detectable current in a current range of ± 18μA, an R2linearity of 0.999, and a dynamic detectable current range of 152dB. The static power consumption of the proposed readout IC is 2.9μW from a 1.5V supply.

This paper presents a self-sustainable landslide surveillance system that detects hazardous water content level in soils and provides real-time landslide warnings to residents, without requiring wired electricity transmission. A self-powered soil water content sensor was applied as the trigger of alert event. It solves the energy supply problem by an environmental interrupt mechanism, which wakes up the sensor and communication circuits in a sensing node only when the water content in monitored soils exceeds a certain threshold, and thus completely eliminates the need for an ALS node to periodically wake up, sense and communicate. By tightly integrating energy harvesting, environment sensing and circuit wake-up, it may well be the most energy-efficient landslide surveillance system designed to monitor water content in soils in the world.

This paper presents a low-power 2.4/5.2GHz concurrent receiver for emerging wireless sensing applications. The RF front-end design includes a concurrent dual-band low noise amplifier (LNA), a stacked mixer and VCO architecture, and variable-gain baseband amplifiers (VGA). Current-reused techniques, by sharing gain stages and stacked components, are explored in the receiver design for the further reduction of power consumption. The prototype chip, which was fabricated in a 0.18μm CMOS process, occupies a chip area of 3.67mm2, including pads and impedance matching networks. At the 2.4GHz band, the proposed receiver achieves a maximum gain of 43dB, a noise figure of 8.9dB, and a 1-dB compression point (P1dB) larger than -34dBm. At the 5.2GHz band, the proposed receiver achieves a maximum gain of 31dB, a noise figure of 16.3dB, and a P1dB larger than -27dBm. The total power consumption is 7.3mW at a supply voltage of 1.2V.

This paper presents a 0.8V analog front-end (AFE) with referenceless time-based digitalization architecture for electrocardiogram (ECG) signal acquisition. Compared to the conventional voltage-domain architecture, the proposed AFE achieves a smaller chip area, lower power consumption, and self-calibration without the high-accuracy clock as well as voltage reference. The chip is fabricated using 0.18μm CMOS technology and occupies a chip area of 0.84 mm2. The design attains a variable gain from 35 dB to 47 dB within a bandwidth of 7 kHz and 10-bit time-to-digital conversion while consuming 43.5 μW at a supply voltage of 0.8V.

This paper presents a wireless on-lens intraocular pressure monitoring system, comprising a capacitance-to-digital converter and a wirelessly powered radio-frequency identification (RFID)-compatible communication system, for sensor control and data communication. The capacitive sensor was embedded on a soft contact lens of 200 μm thickness using commercially available biocompatible lens material, to improve compliance and reduce user discomfort. The sensor chip was shown to achieve effective number of bits greater than 10 over a capacitance range up to 50 pF while consuming only 64-μW power. The on-lens capacitive sensor could detect dielectric variation caused by changes in water content from a distance of 2 cm by using incident power from an RFID reader at 20 dBm. The maximum detectable distance was 11 cm with 30-dBm incident RF power. The rise in eye tissue temperature under 30-dBm RF exposure over an interval of 1 s was simulated and found to be less than 0.01°C.

This paper presents a low-power voltage regulator for wireless sensor nodes. The circuit, implemented in a 90 nm CMOS process, generates a process-temperature-voltage independent 0.5 V while only consuming 26 nA. The output voltage variation is within 27 mV when power supply changes from 1 to 2 V and can provide a 15 μA load current. A fast settling technique is employed to improve the startup response without increasing design complexity.

A multiphase VCO using differential active inductors is designed and fabricated in an IBM 0.13um CMOS process. Using active inductors, the core VCO occupies 0.3×0.4 mm2, and the central frequency can vary from 6GHz to 11GHz, exhibiting a 58% tunable frequency ranges. Exploiting current reuse, the phase noise is measured to be less than −95dBc/Hz at 1MHz offset with the measured power consumption ranging from 12 to 31mW in 6–11GHz. A signal coupling technique with phase shifting is employed to generate eight phase signals. The achieved phase errors of this design are smaller than 3°. In addition, bias compensation is shown to reduce the frequency variation under 10% while the temperature varies from −55°C to 125°C.