In this paper, an advanced duplex scheme, referred to as cross division duplex (XDD), is proposed to use flexible downlink (DL) and uplink (UL) allocation in time division duplex (TDD) carrier. By implementing self-interference cancellation (SIC) functions at the base station, the proposed XDD enables to simultaneously operate UL and DL on different frequency subband in the same channel. To do so, both TDD's ability to efficiently handle asymmetric UL and DL traffic and frequency division duplexing's coverage and latency advantage can be achieved together. To verify the feasibility of XDD, a Proof-of-Concept is developed and self-interference can be removed almost perfectly with proper implementation of SIC without guardband between DL and UL subband. From evaluation results, UL coverage, as well as latency, was improved using a longer UL duty period in XDD. Based on XDD, in 5G-Advanced, a significantly higher resource utilization than the existing 5G will be possible.

In order to verify the system performance of mixed-signal systems on chip (SoCs), computer-aided design (CAD) tools are required to generate 1/f/sup /spl alpha// noise that degrades the performance of most analog circuits. Current techniques for generating discrete sequences of 1/f/sup /spl alpha// noise require a large amount of computations that place an excessive burden on the computation engine and random number generators. In this paper, the authors propose a low-complexity 1/f/sup /spl alpha// noise generation scheme, which is based on a multirate filter bank. In this scheme, each branch in the filter bank processes signals in a different frequency band while allowing for arbitrary selection of /spl alpha/ in each bank. The proposed approach greatly reduces computations when compared to traditional noise generation processes of using a single noise-shaping filter. Furthermore, it allows selecting different combinations of noise frequency response in different frequency bands, thus allowing calibration of noise generated in simulation to the one measured in the laboratory from test chips. A comparison of various noise generation schemes is also presented.

We propose a floorplan-aware complexity reduction methodology for digital filters. Conventional methodologies for complexity reduction use logic-centric approaches focusing on the total number of adders. Therefore, there is a need to consider interconnects to reduce communication costs while synthesizing reduced-complexity filters. In this paper, we integrate high-level synthesis and floorplan to obtain improvement in both computational complexity and interconnect delay. In our experiments, we could achieve 15% improvement in critical-path delay over conventional methodologies.

This paper addresses the design of sigma-delta modulators with arbitrary signal and noise transfer functions by presenting a genetic algorithm (GA) based search method. The objective function is defined to include the difference D between the magnitude of the frequency responses of the designed transfer functions and the ideal one, the quantizer gain /spl lambda//sub critical/ for which the poles of the modulator start moving out of the unit circle, and the spread of the coefficients S. Stability can be improved by reducing /spl lambda//sub critical/ while a smaller S reduces the implementation complexity. A genetic algorithm (GA) searches for poles/zeros of the transfer functions to minimize the objective function D+w/sub 1/*/spl lambda//sub critical/+w2*S, where w/sub 1/ and w/sub 2/ are two weighing factors. Numerical results demonstrate the effectiveness of the proposed method.

RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and HF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct HF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. Software layers are defined to enable these architectures to develop an efficient software defined radio. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.

Finite impulse response (FIR) filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-/spl mu/m technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR filter based on computation sharing multiplier can be reduced to 41% of the FIR filter based on the Wallace tree multiplier for the same frequency of operation.

We present computation reduction techniques which can either be used to obtain multiplierless implementation of finite impulse response (FIR) digital filters or to further improve multiplierless implementation obtained by currently used techniques. Although presented in the FIR filtering framework, these ideas are also directly applicable to any task/application which can be expressed as multiplication of vectors by scalars. The presented approach is to remove computational redundancy by reordering computation. The reordering problem is formulated using a graph in which vertices represent coefficients and edges represent resources required in a computation using the differential coefficient defined by the difference of the vertices joined by the edge. This interpretation leads to various methods for computation reduction for which simple polynomial run time algorithms are presented. It is shown that about 20% reduction in the number of add operations per coefficient can be obtained over the conventional multiplierless implementations. It is also shown that implementations requiring less than one adder per coefficient can be obtained using the presented approaches when using nonuniformly scaled coefficients quantized from infinite precision representation by simple rounding.

In this paper, we present a general approach which specifically targets reduction of redundant computation in common digital-signal processing (DSP) tasks such as filtering and matrix multiplication. We show that such tasks can be expressed as multiplication of vectors by scalars and this allows fast multiplication by sharing computation. Vector scaling operation is decomposed to find the most effective precomputations which yield a fast multiplier implementation. Two decomposition approaches are presented, one based on a greedy decomposition and the other based on fixed-size lookup and this leads to two multiplier architectures for vector-scalar products. Analog simulation of an example multiplier shows a speed advantage by a factor of about 1.85 over a conventional carry save array multiplier. Further simulations using 0.18 /spl mu/ technology show up to 20% speed advantage over Booth encoded Wallace tree multipliers.

This paper presents a factorization based technique to reduce the computational complexity of implementing Finite Impulse Response (FIR) digital filters. It is possible to design FIR filters in which all of the filter coefficients are products of the first seven prime numbers. For such filters, factorization of the filter coefficients allows the reuse of intermediate results among computations involving common factors. Since the coefficients are products of only small prime numbers, it is also possible to generate each of the partial products with a single shift and add operation. Compared to a traditional implementation, this results in a 35-50% reduction in computational complexity, which is shown to translate into lower power consumption.

This paper presents recent trends in the area of integrated CMOS transceiver design for short distance wireless applications. This application is characterized by very low-cost and low-power so-lutions. Current challenges and recent trends are described and digital-oriented design opportunities for increasing integration out-lined. Signal processing approaches applied to the front-end elec-tronics find an increasing emphasis and are extremely viable. 1.

We present a high-level synthesis technique targeting low power consumption for data-dominated applications. We have used a statistical estimation technique to obtain the switching activity of modules when sharing of computing resources are required in a design. The technique enables us to understand the switching behavior under resource sharing. Using the relationship between switching power and resource sharing thus obtained, we developed scheduling and allocation algorithms to reduce the data path switching power. Experiments performed on various examples show up to 49% improvement in power reduction under resource constraints.

We present an architecture of a high performance decision feedback equalizer based on a computation sharing multiplier. The computation sharing multiplier (CSHMR) uses a redundant number scheme and targets removal of computational redundancy by computation re-use. Use of CSHMR leads to high performance FIR filtering operation by re-using optimal precomputations. A decision feedback equalizer (DFE) implementation based on CSHMR in a 0.35 /spl mu/ technology shows 34% improvement in the operating speed over DFE using a Wallace tree multiplier.

In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed and latency remain as the main performance criteria for the target application. The proposed parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 premultiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed, and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18-/spl mu/m L-effective CMOS technology and operates at 550 MSamples/s. Trading off filter latency to improve speed is also discussed.

We present a computation reduction technique which can be used to obtain multiplierless implementations of digital filters without altering their frequency response. The ideas presented are also directly applicable to multiplication of vectors by scalars. The main idea is to expand computation space and reorder computation to maximize computation sharing. It is shown that the reordering problem can be formulated using a graph in which vertices represent coefficients and edges represent resources required in a computation involving the coefficient. The multiplierless solution is obtained by solving a set cover problem on the vertices in the graph. A simple polynomial run time algorithm based on a greedy approach is presented and it is shown that even for large filters (/spl ges/600 taps) less than 1 adder per coefficient can be obtained using the presented methodology.

FIR filtering can be expressed as multiplication of a vector by scalars. We present high-speed implementations for adaptive and nonadaptive filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry save and Wallace tree multipliers in 0.6 /spl mu/ technology. We show that the sharing multiplier scheme improves speed by approximately 30% and 21% with respect to the Wallace tree multiplier based implementation for non-adaptive and adaptive filters, respectively.

In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed remains as the main performance criterion for the target application. A parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 pre-multiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18 µm L-effective CMOS technology and operates at 550 MSamples/s.

We address the issue of high-level synthesis of low-power digital signal processing (DSP) systems by proposing switching activity models. In particular, we present a technology independent hierarchical scheme to compare relative power performance of two competing DSP systems. The basic building blocks considered for such system are a full-adder and a one-bit delay. Estimates of switching activity at the output of these building blocks is used to model the activity in different architectural primitives used for building DSP systems. This method is very fast and simple and simulations show accuracy within 4% of extensive bit-level simulations. Therefore, it can easily be integrated into current communications/DSP CAD tools for low-power applications. The models show that the choice of multiplier/multiplicand is important when using array multipliers in a data-path. If the input signal with smaller variance is chosen as the as the multiplicand, up to 20% savings in switching activity can be achieved. This observation is verified by analog simulation.

Presents novel design methodologies which can be used to dramatically reduce the complexity of parallel implementations of digital FIR filters. These approaches are also applicable to IIR filters. Two ideas are presented. First, we remove the redundant computation by using a graph-theoretic framework in which we find the optimal re-ordering of computations for maximal computation sharing. Second, we present the novel approach of searching for a quantization which improves the computation sharing when the frequency-domain transfer function is allowed to deviate within given bounds. A simple search scheme is presented and it is shown that, by appropriate perturbation of the filter coefficients, one can dramatically reduce the number of adders required in the filter implementation. Using these approaches, on an average, less than one adder per coefficient is required, in contrast to a full-width multiplier. Hence, the presented methodologies are a useful compliment to the existing design approaches of high-performance and low-power digital filters for future mobile computing and communication systems.

This paper presents several new array multiplier architectures for reducing switching activity in general digital signal processing (DSP) applications. A cellular structure is described which can be used to obtain any array multiplier suitable for a given application. The switching activity at the output nodes of the cells in this structure is analyzed and compared with a tree multiplier based on 4:2 compressors. It is shown that the relative improvement in power is a function of statistical properties of the signal and most structures out-perform all others for specific signal conditions. It is also shown that selection of appropriate array architecture can give up to 49% reduction in switching activity compared to a tree multiplier, and more than 3 times less switching activity compared to the widely used least-significant-bit-first array multiplier for commonly occurring situations. We also outline applications of the proposed structures to the areas of low power quantization, reconfigurable computing and high-level synthesis for low power.

We apply constrained least squares solution (CLS) to the problem of reducing the number of operations in FIR digital filters with a motivation of reducing its power consumption. The constraints are defined by the maximum allowable add/subtract operations in forming the products which are used in computing the output. We show that truncation and rounding of coefficients can be viewed as power constrained least squares (PCLS) solutions. Further, we show that in dedicated DSP processor based architectures it is possible to reduce power by using PCLS coefficients along with appropriately modified multipliers. It is also shown that the Booth multiplier effectively reduces the complexity of such filters, thereby increasing power savings. Finally, we show that typically 80% to 45% reduction in number of operations can be obtained for systems employing uncoded and Booth recoded multipliers, respectively.

Code-division multiple access (CDMA) has found widespread applications in various applications such as advanced wireless technologies and digital cellular communications. We consider the error-rate performance of asynchronous direct-sequence CDMA in a wireless radio communications environment that is characterized by Rayleigh multipath fading channels. Because of the system complexity, the performance of CDMA systems in such an environment is difficult to assess analytically. Monte Carlo simulations can offer an alternative performance evaluation tool. Unfortunately, in practice, such an alternative is often limited by an excessive computational burden. Importance sampling is a variance reduction technique which can significantly reduce the computational cost required by Monte Carlo simulations. This paper describes the basic principles behind this powerful technique. In particular, it illustrates its use as a computationally efficient and accurate tool for computer-aided design and analysis of uncoded as well as coded CDMA in wireless communications.

Sequential decoding is a very powerful decoding procedure for convolutional codes which is characterized as a sequential search for the correct transmitted path through a large decision tree with random node metrics. The authors present a new efficient technique for accurately estimating the bit error rates (BERs) of stack or Zigangirov-Jelinek (ZJ) sequential decoders for specific time-invariant convolutional codes. In contrast to a brute-force simulation approach, this method achieves computational efficiency by using a mean-translation importance sampling biasing method along with a set of easily checked rules which immediately eliminate the need of running the computationally intensive ZJ algorithm in a large number of simulation trials.>

This paper presents new computationally efficient and accurate techniques for estimating the performance of specific high-rate punctured convolutional codes and uses these techniques to evaluate the performance of sequential and Viterbi decoders for the best known codes. In particular, it demonstrates that the disparity between sequential and Viterbi decoding increases dramatically for long memory codes with high rates and for such codes, the union bound cannot be used as a criterion for selecting good codes for sequential decoders. In contrast, it shows that the proposed methods can be used as efficient tools for performance evaluation and/or identification of good high-rate punctured convolutional codes for use with sequential decoders.