In modern processors, deep pipelines couple with superscalar techniques to allow each pipe stage to process multiple instructions. When such a pipe must be pushed and refilled, as when predicted program flow beyond a branch is subsequently recognized as wrong, the temporary performance loss is significant. While modern branch target buffer (BTB) technology makes this flush/refill penalty fairly rare, the penalty that accrues from the remaining branch mispredictions is a serious impediment to even higher processor performance. Advanced mechanisms that can reduce this residual misprediction penalty can be of enormous value in future microprocessor designs. One promising new mechanism, the Misprediction Recovery Cache (MRC) is proposed previously. In this paper, we focus especially on MRC integration into existing pipelines.

In tomorrow's 'brilliant' weapons, next-generation avionic computers will need to orchestrate the actions of many subsystems while further maintaining the security of sensitive data, the integrity of key data and of system behavior, and often other key properties. Maintenance of these properties will help ensure that system execution is trustable, conforming to both prescribed policies and expected behavior. The essential properties of security and integrity are introduced, and other properties (like virus resistance) that should complement them in future avionic computing are cited. Traditional security maintenance as derived from simple controls that constrain application accesses in a rather rigid way are reviewed. It is illustrated how, to add integrity maintenance capability, such controls can be enhanced to support customizable application execution constraint. Mechanisms for supporting security and integrity in next-generation avionic architectures are recommended.>

An architecture especially adept at security support is outlined. The architecture's fundamental information unit is a two-tuple, or ordered pair, consisting of a datum word and an associated security tag. As an atomic information unit, the two-tuple moves around through the architecture in unison as processing proceeds. a security subprocessor always operates on a security tag in synchrony with a fairly ordinary data subprocessor's operation on the associated datum word. The coupled subprocessors provide the overall architecture with efficient, multilevel-secure access control and flow control. The proposed architecture represents the advancement of security technology along a unique combination of three fronts: (1) direct hardware support, (2) fine-grained-to-the-word mediation, and (3) optimal (minimal) result classification. >

This paper discusses an algorithm for optimizing the density and parallelism of microcoded routines in microprogrammable machines. Besides the algorithm itself, the algorithm's uses, adaptability to conventional machine characteristics, and architectural requirements are also discussed and analyzed. Even though the paper proposes a hardware implementation of the algorithm, the algorithm is viewed as an integral part of the entire microcode generation and usage process, from initial high-level input into a software microcode compiler down to machine-level execution of the resultant microcode on the host machine. It is believed that, by removing much of the traditionally time-consuming and machine-dependent microcode optimization from the software portion of this process, the algorithm can improve the overall process.