EDBT 2026 Demo / reviewers in the wild / expert
Kevin Stevens
dblp:51/3262
· DBLP profile ↗
2ranked-venue papers
1as first author
1since 2021 · last 2024
0009-0008-3832-4058ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Security and privacy · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs › FPGA architecture
adaptive logic module |
0.1 | 1 | 2005 | The Stratix II logic and routing architecture · FPGA 2005 |
Reconfigurable computing and FPGAs
FPGA routing architecture |
0.1 | 1 | 2005 | The Stratix II logic and routing architecture · FPGA 2005 |
Methods — techniques the papers use, named apart from their topics
arithmetic structure design · 0.1LUT partitioning · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | BluePrint: Automatic Malware Signature Generation for Internet ScanningabstractTraditional malware-detection research has focused on techniques for detection on end hosts or passively on networks. In contrast, global malware detection on the Internet using active Internet scanning remains relatively unstudied, with research still relying on manual reverse engineering and handwritten scanning code. Kevin Stevens, Mert Erdemir, Hang Zhang 0012, Taesoo Kim, Paul Pearce |
RAID | 1 |
| 2005 | The Stratix II logic and routing architectureabstractThis paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration. David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose |
FPGA | 20 |