Analog circuits are designed in fundamentally different ways than their counterparts in the digital domain. However, two major trends have made analog and digital circuits mix and co-exist. First, high-performance analog circuits use digital parts and vice versa. Second, the desire for new features, ease of use and reducing integration costs brings together more digital, analog and RF circuits in one die. This convergence of circuits creates a significant need for analog and digital layout tools to also unify. The first such solution the EDA industry provides is Magma's Titan design platform [1]. In this extended abstract, we describe how Titan speeds up mixed signal circuit and layout design with new capabilities and a new level of integration of tools

Faced with continually coping with Moore's Law, computer-aided design (CAD) for integrated circuits is used to facing challenges in our ever-evolving design problem. Increasing device complexity is a perennial challenge and has led to several discontinuities in design methodology. Over the last decade deep submicron physical effects have significantly complicated the design process and required new efforts in design for manufacturability. With the emergence of multicore and manycore microprocessor systems we face a new type of challenge: Not only will our design object (the microprocessor systems themselves) take another leap in complexity, but for the first time in our industry's history we will need to fundamentally change the way we design and implement our software solutions as well. In this panel a broad set of representatives at the front lines of addressing this challenge will outline how they plan to respond. Representative questions to the panelists include:

Variability in process parameters leads to a significant parametric yield loss of high-performance ICs due to the large spread in leakage-power consumption and speed of chips. In this paper, we propose an algorithm for total power minimization under timing constraints in the presence of variability. The algorithm is formulated as a robust optimization program with a guarantee of power and timing yields, with both power and timing metrics being treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold-voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. The performance of the algorithm was evaluated on a variety of public and industrial benchmarks, with a library characterized using 70-nm Berkeley Predictive Technology Model. When compared to the deterministic optimization, the new algorithm, on average, reduces static power and total power at the 99.9th quantile by 31% and 17%, respectively, without loss of parametric yield. The run-time on the benchmarks is 30times faster than other known statistical power-minimization algorithms.

Sakurai-Newton (SN) delay metric (Sakurai, 1990) is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that the SN metric fails to provide high accuracy and fidelity when CMOS gates operate at low supply voltages. Thus it may not be applicable in many low power applications with voltage scaling. In this paper, we propose a new closed form delay metric based on the centroid of power dissipation. This new metric is inspired by our key observation and theoretic proof that the SN delay is indeed Elmore delay, which can be viewed as the centroid of current. Our proposed metric has a very high correlation coefficient (ges 0.98) when correlated with the actual delays got from the HSPICE simulations. Such high correlation is consistent across all major process technologies. In comparison, the SN metric has a correlation coefficient between (0.70, 0.90) depending upon the technology and the CMOS gate, and it is less accurate for lower supply voltages. Since our proposed metric has high fidelity across a wide range of supply voltages yet a simple closed form, it is very useful to guide low voltage and low power designs

In addition to traditional constraints on frequency, leakage current has emerged as a stringent constraint in modern processor designs. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must consider the dependence of leakage current on frequency. In this paper, a new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability is presented. A closed-form equation for total chip leakage that models the dependence of the leakage current distribution on different process parameters is developed. The proposed analytical expression is obtained directly from pertinent design information and includes both subthreshold and gate leakage currents. Using this model, an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design is then presented. The proposed method demonstrates the importance of considering both these limiting factors while calculating the yield of a lot

In this paper, we present a novel approach to obtain any desired intermediate threshold voltage in a dual VT process. The intermediate threshold voltages are achieved by combining low and high threshold voltages in a device. We show that this combination can be easily implemented in layouts with negligible design and manufacturing overhead. Our results show that power-delay characteristics of the achieved intermediate thresholds match well with the ideal (but impractical) scenario that assumes that all intermediate thresholds are available in the technology.

Leakage power is emerging as a key challenge in IC design. Leakage is increasingly exponentially with each technology generation and is expected to become the dominant part of total power. Device threshold voltage scaling, shrinking device dimensions, and larger circuit sizes are causing this dramatic increase in leakage. As leakage varies exponentially with process parameters, yield of the chip is often directly influenced by leakage. Increasing amount of leakage is also critical for power constraint ICs. Traditionally, leakage has been considered as an important design variable in handheld devices and in standby circuit operation. However, this significant increase of leakage now warrants that it be considered as the key design variable in all IC designs.This tutorial presents a comprehensive review of leakage power issues in IC design. The tutorial is organized in four major parts. The first part provides an overview of technology and scaling trends which are causing the significant increase in leakage current. The device physics that leads to sub-threshold and gate leakage will be described, along with their dependence on circuit design variables. This part of the tutorial will also cover basic transistor and circuit techniques to minimize leakage, such as the stack effect.The second part of the tutorial will focus on circuit level leakage estimation and avoidance. Use of multiple threshold voltages has been very successful in controlling the leakage of the circuit. Comprehensive description of multiple-Vt techniques for leakage avoidance will be presented along with associated leakage estimation techniques. Multiple-threshold design (MTCMOS) will be described along with its leakage benefits and performance trade-offs. Multiple oxide technology options and associated impact on gate leakage will also be discussed.Third part of the tutorial focuses on chip level effects on leakage. Leakage is heavily dependent on local and global process variations and can vary by an order of magnitude over the technology spread. Leakage estimation techniques which consider both inter and intra-die process variations will be covered. This part of the tutorial also focuses on chip-level leakage minimization techniques. Leakage minimization techniques such as Adaptive Body Bias (ABB) and power supply control will be presented.The last part of the tutorial covers system and circuit architectures for leakage avoidance. In standby mode, the leakage of the circuit can be lowered by putting it a low-leakage state. Caches and memory circuits occupy large percentage of area in model chips. The leakage of caches and memories need to be carefully controlled. This section of the tutorial will cover topics including state assignment for leakage minimization, leakage-driven memory and cache circuits and architectures.The tutorial is intended for designers and CAD engineers interested in next generation design techniques and methodologies and emerging power challenges. Basic background of VLSI and CAD is useful though not needed.

Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to gate the power supply. This paper presents a new methodology based on timing criticality and temporal currents to size the sleep transistor. The timing criticality information and temporal current estimation are obtained using static timing analyzer. The results obtained indicate that our proposed technique results in area reduction of sleep transistors by 80% and 49% compared to module based design and cluster based design respectively.

Spatially distributed 3D circuit models are extracted with a segment-to-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather than using the traditional net-to-net approach. Critical issues regarding the extraction efficiency and accuracy of segment-to-segment BEM capacitance models are explored. An adaptive discretization scheme is developed for segment-to-segment capacitance extraction and also applied to segment-to-segment high-frequency inverse inductance extraction. We demonstrate the limitations of the duality between capacitance and inverse inductance. Examples demonstrating the accuracy of these models are presented for real packaging cases.

Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. When compared to the deterministic optimization, the new algorithm, on average, reduces static power by 31% and total power by 17% without the loss of parametric yield. The run time on a variety of public and industrial benchmarks is 30X faster than other known statistical power minimization algorithms.

Full-chip verification requires one to check if the power grid is safe, i.e., if the voltage drop on the grid does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verification of the grid. We propose a power grid verification technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. Based on this, we propose two solution approaches. One approach gives an upper-bound on the worst-case voltage drop at every node of the grid. Another, less expensive approach, applies a sufficient condition (thus, this becomes a conservative approach) to check if the drop on the grid exceeds a given voltage threshold

Leakage current has become a stringent constraint in modern processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must consider the dependence of leakage current on frequency. In this paper, we present a new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability. We develop a closed-form expression for total chip leakage that models the dependence of the leakage current distribution on a number of process parameters. The model is based on the concept of scaling factors to capture the effects of within-die variability. Using this model, we then present an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design. Our method demonstrates the importance of considering both these limiters in calculating the yield of a lot.

For optimizations like physical synthesis and static timing analysis, efficient interconnect delay and slew computation is critical. Since one cannot often afford to run asymptotic waveform evaluation (Pillage and Rohrer, 1990), constant time solutions are required. This work presents the first complete solution to closed-form formulas for both delay and also for slew. Our metrics are derived from matching circuit moments to the lognormal distribution. From a single table, one can easily implement the metrics for delay and slew for both step and ramp inputs. Experiments validate the effectiveness of the metrics for nets from a real industrial design.

Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these formulae assume a step excitation, leaving it to the reader to find a suitable extension to ramp-we always refer to saturated ramps in this paper-inputs. The few works that do consider ramp inputs do not present a closed-form formula that works for a wide range of possible input slews. We propose the PERI (probability distribution function extension for ramp inputs) technique, that extends delay metrics for step inputs to the more general and realistic non-step (such as a ramp) inputs. Although there has been little work done in finding good slew (which is also referred as signal transition time) metrics, we also show how one can extend a slew metric for step inputs to the non-step case. We validate the efficacy of our approach through experimental results from several hundred RC dominated nets extracted from an industry application specific integrated circuit design.

For optimizations like physical synthesis and static timing analysis, efficient interconnect delay and slew computation is critical. Since one cannot often afford to run AWE[12], constant time solutions are required. This work presents the first complete solution to closed form formulae for both delay and slew. Our metrics are derived from matching circuit moments to the lognormal distribution. From a single table, one can easily implement the metrics for delay and slew for both step and ramp inputs. Experiments validate the effectiveness of the metrics for nets from a real industrial design.

Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate system power. This paper describes a static (i.e input independent) technique for efficient and accurate leakage estimation. A probabilistic technique is presented to compute the average leakage of combinational circuits. The proposed technique gives accurate results with an average error of only 2% for the ISCAS benchmarks and accurately predict both subthreshold and gate leakage as well as the leakage sensitivities to process and environmental parameters.

Gate leakage current is expected to be the dominant leakage component in future technology generations. In this paper, we propose methods for steady-state gate leakage estimation based on state characterization. An efficient technique for pattern-dependent gate leakage estimation is presented. Further, we propose the use of this technique for estimating the average gate leakage of a circuit using pattern-independent probabilistic analysis. Results on a large set of benchmark ISCAS circuits show an accuracy within 5 % of SPICE results with 500X to 50000X speed improvement.

Leakage power is emerging as a key design challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations. State of the art techniques are used to compute the thermal and power supply profile of the entire chip. Closed-form models are presented which relate leakage to temperature and VDD variations. These models coupled with the thermal and VDD profile are used to generate an accurate full chip leakage estimation technique considering environmental variations. The results of this approach are demonstrated on large-scale industrial designs.

Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these formulae assume a step excitation, leaving it to the reader to find a suitable extension to ramp inputs (we always assume a saturated ramp in this paper). The few works that do consider ramp inputs do not present a closed-form formula that works for a wide range of possible input slews. We propose the PERI (Probability distribution function Extension for Ramp Inputs) technique, that extends delay metrics for step inputs to the more general and realistic non-step inputs. Although there has been little work done in finding good slew - which is also referred as signal transition time - metrics, we also show how one can extend a slew metric for step inputs to the non-step case. We validate the efficacy of our approach through experimental results from several hundred RC dominated nets extracted from an industry ASIC design.

On-chip inductance extraction is difficult due to the global effect of inductance, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore, it is well known that simply discarding smallest terms to sparsify the inductance matrix can render the partial inductance matrix indefinite and result in an unstable circuit model. Recently a new circuit element, K , has been introduced to capture global effect of inductance by evaluating a corresponding sparse K matrix [1]. However, the reason that K has such local properties is not clear, and the positive semi-definiteness of the corresponding sparse K matrix is not proved. In this paper, we present the physical interpretation of K. Based on the physical interpretation, we explain why the faraway mutual K can be ignored (locality) and prove that after ignoring faraway mutual K ,the resultant K matrix is positive definite (stability). Together with a RKC equivalent circuit model, the locality and stability enables us to simulate RKC circuit directly and efficiently for real circuits. A new circuit simulation tool, KSim, has been developed by incorporating the new circuit element K into Berkeley SPICE. The RKC simulation matches better with the full partial inductance matrix simulation with significant less computing time and memory usage, compared to other proposed methods, such as shift-truncate method [2, 3].

Interconnect synthesis techniques, such as wire sizing and buffer insertion/sizing, have proven to be critical for reducing interconnect delays in deep submicron design. Consequently, the past few years have seen several works that study buffer insertion, wire sizing, and their simultaneous optimization. For long interconnect, wire tapering, i.e., reducing the wire width as the distance from the driver increases, can yield better solutions than uniform wire sizing. However, despite its obvious benefits, tapering is not widely used in practice since it is difficult to integrate into a coherent routing methodology. This paper studies the benefits of wire sizing with tapering when combined with buffer insertion. We first present a theoretical result that shows wire tapering is at most 3.5% faster than uniform wire sizing when maximal buffer insertion is applied. We then present detailed experiments that support this result. Consequently, we conclude that it is generally not worthwhile to perform tapering for signal nets. Finally, we present a general formulation and optimal polynomial time algorithm for simultaneous wire sizing and buffer insertion that forbids wire tapering, but incorporates layer assignment and wire spacing.

For performance optimization tasks such as floorplanning, placement, buffer insertion, wire sizing, and global routing, the Elmore resistance-capacitance (RC) delay metric remains popular due to its simple closed form expression, fast computation speed, and fidelity with respect to simulation. More accurate delay computation methods are typically central processing unit intensive and/or difficult to implement. To bridge this gap between accuracy and efficiency/simplicity, we propose two new RC delay metrics called delay via two moments (D2M) and effective capacitance metric (ECM), which are virtually as simple and fast as the Elmore metric, but more accurate. D2M uses two moments of the impulse response in a simple formula that has high accuracy at the far end of RC lines. ECM captures resistive shielding effects by modeling the downstream capacitance by an "effective capacitance." In contrast, the Elmore metric models this as a lumped capacitance, thereby ignoring resistive shielding. Although not as accurate as D2M, ECM yields consistent performance and may be well-suited to optimization due to its Elmore-like recursive construction.

On-chip inductance extraction and analysis is becoming increasing critical. Inductance extraction can be difficult, cumbersome and impractical on large designs as inductance depends on the current return path-which is typically unknown prior to extracting and simulating the circuit model. In this paper we propose a new circuit element, K, to model inductance effects, at the same time being easier to extract and analyze. K is defined as inverse of partial inductance matrix L, and has locality and sparsity normally associated with a capacitance matrix. We propose to capture inductance effects by directly extracting and simulating K, instead of partial inductance, leading to much more efficient procedure which is amenable to full chip extraction. This proposed approach has been verified through several simulation results.

Efficient, yet accurate delay estimation for RC interconnect is required for the optimization loop of timing driven physical design tools. For many applications, the Elmore delay metric has been widely used due to its efficiency and ease of use. However, it is well known that the Elmore metric can have significant error since it ignores the resistive shielding of downstream capacitance. We present a new interconnect metric called ECM that accounts for this resistive shielding by computing an effective capacitance to model the downstream capacitance. ECM can also be computed with the same complexity as the Elmore delay and does not require the computation of moment. Experiments show that ECM is significantly more accurate than Elmore delay and is competitive with other metrics that use multiple moments.

For performance optimization tasks such as floorplanning, placement, buffer insertion, wire sizing, and global routing, the Elmore RC delay metric [3] remains popular due to its simple closed form expression, fast computation speed, and fidelity with respect to simulation.More accurate delay computation methods are typically either CPU intensive or difficult to implement.To bridge this gap between accuracy and simplicity, we propose the D2M RC delay metric, which is virtually as simple and fast as the Elmore metric but is significantly more accurate.The new metric is theoretically bounded above by the Elmore delay, yet it rarely is more than a few percent below the actual delay.Consequently, the metric behaves like the Elmore metric in that it generally overestimates delay, but with consistently less error.Further, the metric is extremely accurate at the far end of RC lines.

This paper presents a general method for computing transient sensitivities using both direct and adjoint methods in controlled explicit event driven simulation algorithms that employ piecewise linear device models. Sensitivity information provides first order assessment of circuit variability with respect to design variables and parasitics. This information is particularly useful for noise analysis, timing rule generation, and circuit optimization. Techniques for incorporating transient sensitivity into adaptively controlled explicit simulation, a general piecewise linear simulator, are presented. Sensitivity computation includes algorithms to handle instantaneous charge redistribution due to the discontinuous conductance models of the piecewise linear elements, and the loss of simulation accuracy due to the nonmonotonic responses in autonomous adjoint circuits with nonzero initial conditions. Results demonstrate the efficiency and accuracy of the proposed techniques.

Article Free Access Share on Buffer insertion with accurate gate and interconnect delay computation Authors: Charles J. Alpert IBM Austin Research Laboratory, Austin, TX IBM Austin Research Laboratory, Austin, TXView Profile , Anirudh Devgan IBM Austin Research Laboratory, Austin, TX IBM Austin Research Laboratory, Austin, TXView Profile , Stephen T. Quay IBM Server Group, Austin, TX IBM Server Group, Austin, TXView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 479–484https://doi.org/10.1145/309847.309983Published:01 June 1999Publication History 46citation557DownloadsMetricsTotal Citations46Total Downloads557Last 12 Months38Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Wire sizing and buffer insertion/sizing are critical optimizations in deep submicron design. The past years have seen several studies of buffer insertion, wire sizing, and their simultaneous optimization. When wiring long interconnect, tapering, i.e., reducing the wire width as the distance from the driver increases, has proven effective. However tapering is not widely utilized in industry since it is difficult to integrate into a complete routing methodology. The article examines the benefits of wire sizing with tapering when combined with buffer insertion. We perform several experiments with actual IBM technologies. Results indicate that wire tapering reduces delay typically by less than 5% compared to uniform wire sizing, when buffers can be inserted. Consequently, we suggest that it may not be worthwhile to maintain a routing methodology that supports wire tapering.

Interconnect reduction is an important step in the design and analysis of complex interconnects found in present-day integrated circuits. This paper presents techniques for obtaining realizable and accurate reduced models for two-port and multi-port RC circuits. The proposed method is also particularly suitable for interconnect reduction for nonlinear circuit simulation and for interconnect post-processing in a parasitic extractor. The method has two limitations. First, it only considers the first few moments of the transfer function; however that is accurate enough for RC circuits. Second, the amount of interconnect reduction is topology dependent. Although, most on-chip interconnect topologies are well suited for the method proposed. Accuracy and efficiency of the proposed method is demonstrated for various realistic examples.

Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in global interconnect paths; however, existing techniques only optimize delay and timing slack, With the continually increasing ratio of coupling capacitance to total capacitance and the use of aggressive dynamic logic circuit families, noise analysis and avoidance is becoming a major design bottleneck. Hence, timing and noise must be simultaneously optimized to achieve maximum performance. This paper presents comprehensive buffer insertion techniques for noise and delay optimization. Three algorithms are presented, the first for noise avoidance for single sink trees, the second for avoidance for multiple sink trees, and the last for simultaneous noise and delay optimization. We prove the optimality of each algorithm (under various assumptions) and present other theoretical results as well. We ran experiments on a high-performance microprocessor design and show that our approach fixes all noise violations, Our approach was separately verified by a detailed, simulation-based noise analysis tool. Further, we show that optimizing delay alone cannot fix all of the noise violations and that the performance penalty induced by optimizing both delay and noise as opposed to only delay is less than 2%.

Timing analysis spans the entire design process from RTL synthesis to timing sign-off including schematic design, logic synthesis, floor plan, place and route, clock distribution etc. In this embedded tutorial we will cover timing analysis from devices to systems. At the transistor level we will cover static, dynamic and interconnect analysis. At the gate level we will cover path analysis including false paths and static and dynamic sensitization aspects. The new Delay Calculator Language (DCL) will also be covered. We will tie the statistical properties at each level to put them under proper perspective.

Buffer insertion has successfully been applied to reduce delay in global interconnect paths; however, existing techniques only optimize delay and timing slack. With the increasing ratio of coupling to total capacitance and the use of aggressive dynamic logic circuit families, noise is becoming a major design bottleneck. We present comprehensive buffer insertion techniques for noise and delay optimization. Our experiments on a microprocessor design show that our approach fixes all noise violations that were identified by a detailed, simulation-based noise analysis tool. Further, we show that the performance penalty induced by optimizing both delay and noise as opposed to only delay is 2%.

This paper presents a general method for computing transient sensitivities using the adjoint method in event driven simulation algorithms that employ piecewise linear device models. Sensitivity information provides first order assessment of circuit variability with respect to design variables and parasitics. This information is particularly useful for noise stability analysis, timing rule generation, and circuit optimization. Techniques for incorporating adjoint transient sensitivity into ACES, a general piecewise linear simulator, are presented. Sensitivity computation includes algorithms to handle instantaneous charge redistribution due to the discontinuous conductance models of the piecewise linear elements, and the loss of simulation accuracy due to the non-monotonous responses in autonomous adjoint circuits with non-zero initial conditions. Results demonstrate the efficiency and accuracy of the proposed techniques.

Thispaperpresents a matrLrpartitioning scheme for the simulation of coupling capacitances in timing and noise analysis.An error criten.onsimilar to the local truncation error of integration algorithms was developed to control the error due to this matriv partitioning algorithm.~e major advantage of the algorithm is that it does not require iterations such as required in rela~ation algon.thrns,and it is designed to work with circuit partitioning for eficient simulation of large circuits in fast circuitkiming simulator like ACES [lJ, which firms the basis for an eficient transistor level simulation and analysis.The mattipartitioning algorithm alsofits well with controlled evplicit integration algon"thms.Results demonstrate that the algon.thmcan ensure simulation accuracy without signl~cantly degrading simulation eficiency for the timing and noise analysis of circuits designed in advanced technologies with small feature sizes.

Buffer insertion seeks to place buffers on the wires of a signal netto minimize delay. Van Ginneken [Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay] proposed an optimal dynamicprogramming solution (with extensions proposed by [7] [8][9] [12]) such that at most one buffer can be placed on a singlewire. This constraint can hurt solution quality, but it may be circumventedby dividing each wire into multiple smaller segments.This work studies the problem of finding the correct number of segmentsfor each wire in the routing tree. Too few segments yieldssub-par solutions, but too many segments can lead to excessive runtimes and memory loads. We derive new theoretical results forcomputing the appropriate number of buffers (and hence wire segments)which motivate our new wire segmenting algorithm. Weshow that using wire segmenting as a precursor to buffer insertionproduces solutions within a few percent of optimal, while usingonly seconds of CPU time.

Noise analysis and avoidance is an increasingly critical step in deep submicron design. Ever increasing requirements on performance have led to widespread use of dynamic logic circuit families and its other derivatives. These aggressive circuit families trade off noise margin for timing performance making them more susceptible to noise failure and increasing the need for noise analysis. Currently, noise analysis is performed either through circuit or timing simulation or through model order reduction. These techniques in use are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuits. This paper presents efficient techniques for estimation of coupled noise in on-chip interconnects. This noise estimation metric is an upper bound for RC circuits, being similar in spirit to Elmore delay in timing analysis. Such an efficient noise metric is especially useful for noise criticality pruning and physical design based noise avoidance techniques.

This paper presents a general method for incorporating state transformation in event driven explicit simulation. One inherent assumption in this type of simulation algorithm is the state independence, which allows the algorithm to process the states independently in an event driven manner at the transistor level. Numerical problems arise when an inappropriate state representation of the circuit, in which the states are not truly independent, is chosen. In principle, any similarity transformation of the state equation can be employed to transform the circuit into a more convenient state space for numerical solution. This paper develops a systematic scheme to derive an appropriate state transformation, and to incorporate the state transformulation in such a way to maintain the efficiency of event driven explicit simulation algorithms.

Transient simulation has traditionally been performed in the current-voltage plane (with current and voltage as variables) for verification of integrated circuits and systems. This paper introduces techniques for efficient and accurate transient simulation in the charge-voltage plane (with charge and voltage as variables). For integrated circuits, both simulation cost and overhead to increase accuracy are drastically reduced by performing simulations in the charge-voltage plane. Adaptively controlled explicit simulation in charge-voltage plane is used to demonstrate the feasibility of the approach. Solution of circuit equations in the charge-voltage plane is 10-20 times more efficient than in the current-voltage plane. Furthermore, simulation accuracy can be increased at an incremental cost. As a result, ACES in the charge-voltage plane provides speedups of 300/spl times/-5000/spl times/ or more over traditional circuit simulators with little or no loss in circuit timing accuracy, and simulates circuits containing more than million transistors.

Transient simulation has traditionally been performed in current-voltage plane (with current and voltage as variables)for verification of integrated circuits and systems. This paper introduces techniques for efficient and accurate transient simulation in charge-voltage plane (with charge and voltage as variables). For integrated circuits, both simulation cost and overhead to increase accuracy are drastically reduced by performing simulations in charge-voltage plane. Adaptively controlled explicit simulation in charge-voltage plane is used to demonstrate the feasibility of the approach. Solution of circuit equations in charge-voltage plane is 10-20 times more efficient than in current-voltage plane. Furthermore, simulation accuracy can be increased at an incremental cost. As a result, ACES in charge-voltage plane provides speedups of 300/spl times/-5000/spl times/ or more over traditional circuit simulators with little or no loss in circuit timing accuracy.

Accuracy of a transient simulator is critically dependent on its device models, and device model evaluation is often a bottleneck in transient simulation performance. This paper presents comprehensive modeling techniques to compute Fast-to-evaluate and Accurate Simplified Transistor (FAST) models for aggressive MOS technologies. These FAST models accurately capture the static and dynamic behavior of the transistor, and lend themselves to efficient transient simulation. Use of FAST models in timing simulator AGES leads to speedups of 1000/spl times/ or more over traditional circuit simulators with little or no loss in circuit timing accuracy.

Adaptively Controlled Explicit Simulation (ACES) is a timing simulation methodology for the verification of the transient behavior of integrated circuits. A new adaptively controlled explicit integration approximation is used that overcomes stability problems encountered in earlier explicit techniques. Circuit partitioning is employed, which allows event driven simulation and exploitation of circuit latency. Piecewise linear models are used for nonlinear devices, allowing efficient simulation of MOS, bipolar, and BiMOS circuits. Simulation accuracy in ACES can be varied by controlling the accuracy of either the integration approximation or the piecewise linear device models. With the combination of generality, exploitation of circuit latency, and ability to vary accuracy effectively, ACES provides an efficient environment for transient simulation of integrated circuits and systems.>

Adaptively Controlled Explicit Simulation (ACES) is a timing simulation methodology for integrated circuits and systems. The paper presents the use of event driven simulation and partitioning to enhance the ACES simulation environment by exploiting the latency present in integrated circuits. ACES also uses an improved, adaptively controlled explicit integration approximation which overcomes the stability problems encountered in earlier explicit techniques. Piecewise linear models are used for nonlinear devices allowing efficient simulation of MOS, BiMOS and bipolar circuits.

Adaptively Controlled Explicit Simulation (ACES) is a transient simulation methodology for integrated circuits and systems. An adaptively controlled explicit integration approximation is used which overcomes the stability problems encountered in earlier explicit techniques. Piecewise linear models are used for nonlinear devices, which allows efficient simulation of MOS, bipolar and BiMOS circuits. With the combination of generality, exploitation of circuit latency and ability to vary accuracy effectively, ACES provides an efficient environment for transient simulation of integrated circuits and systems.>