Load shift keying (LSK) is commonly used in wireless power transfer (WPT) systems for backscattering information from the receiver back to the transmitter. However, when the coupling coefficient (k) between the coupling coils falls below a threshold value (kDF), the demodulated LSK data can unexpectedly flip from '1' to '0' and '0' to '1'. This phenomenon is referred to as coupling-dependent data flipping (CDDF). This research investigates the factors that lead to CDDF in series-series resonant WPT systems, by taking into account of parasitic parameters of the coupled link and validates the analysis through SPICE simulations. To mitigate CDDF, we propose a carrier-frequency auto-tuning scheme that is also verified by simulation results.

A fully-integrated reconfigurable switched-capacitor converter (SCC) that achieves very low voltage conversion ratios (1/4X, 1/5X and 1/6X) in a 65nm CMOS process is presented. It has three topological phases, and the SCC achieves minimum output resistance for every topology. An analysis is proposed to optimize the system efficiency with the consideration of charge redistribution loss, conduction loss, gate drive loss and bottomplate parasitic loss.

This paper presents a 13.56MHz active rectifier used in a wireless power transfer system for implantable medical devices that employs digital-to-time converters in replacing analog comparators to generate delay-compensated gate control signals for the power transistors. The low-power digital controller employs a successive approximation register (SAR) to generate digital codes for delay compensation, achieving zero-voltage switching and eliminating reverse conduction loss. Fabricated in a standard 65nm CMOS process, the proposed rectifier has an active area of 0.02mm2. The quiescent power is$13.6\mu $W, 15 times lower than the traditional design. The power transfer efficiency is maintained above 90% from 3mW to 40mW with maximum efficiency of 95% at 16mW. Under light load condition, the proposed design achieves more than 20% efficiency enhancement compared to the rectifier without delay compensation.

In this research, we introduce a hybrid power converter for point-of-load (PoL) applications. By separating the DC-DC converter into two stages, this hybrid converter achieves a voltage conversion ratio of D2/2. Therefore, 5V power transistors can be used in the main current path, which significantly increases efficiency. An adaptive dead-time control and an anti-shoot-through buffer are proposed to further enhance efficiency. With VIN=24V and VOUT=1V, this converter achieves a peak efficiency of 94.5% at 1A output.

A low-power CMOS voltage reference with active-feedback frequency compensation is proposed for power-constrained IoT applications whereby power supply ripple rejection (PSRR) performance is critical for the survival of the devices. The proposed voltage reference consists of MOS transistors operating in the sub-threshold region to allow for low-voltage and low-power operations. An active-feedback frequency compensation technique has been used to make the loop stable and improve the PSRR with a very small compensation capacitor while allowing a relatively large output capacitor. The circuit is fabricated in a standard 0.18-μm CMOS process. The measured power consumption is 22nW at 0.7V power supply. The measured temperature coefficient (TC) is 38ppm/°C in a range from -40 to +110°C, and the line regulation is 200μV/V in a supply voltage range of 0.7~2V. The measured PSRR at 10 Hz, 1 kHz, and 100 kHz is -64dB, -56dB, and -52dB, respectively. The active chip area is 0.04mm2.

This brief presents a novel ultralow power CMOS voltage reference (CVR) with only 4.6-nW power consumption. In the proposed CVR circuit, the proportional-to-absolute-temperature voltage is generated by feeding the leakage current of a zero-Vgs nMOS transistor to two diode-connected nMOS transistors in series, both of which are in subthreshold region; while the complementary-to-absolute-temperature voltage is created by using the body diodes of another nMOS transistor. Consequently, low-power operation can be achieved without requiring resistors or bipolar junction transistors, leading to small chip area consumption. The proposed CVR circuit is fabricated in a standard 0.18-μm CMOS process. Measurement results show that the prototype design is capable of providing a 755 mV typical reference voltage with 34 ppm/°C from -15 °C to 140 °C. Moreover, the typical power consumption is only 4.6 nW at room temperature and the active area is only 0.0598 mm2.