This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.

This paper describes a new algorithm for the placement of analog modules. The algorithm is a hybrid of greedy partitioning and mean field annealing techniques. The sensitivities of performance functions are used to compute the changes in the functions during the placement process. The objective function is designed to incorporate the effect of the performance functions in terms of their slacks beyond the design constraints along with other requirements such as area and aspect ratio. The algorithm has been implemented and results are tested for seven commercial bipolar circuits.>

Synapse, neuron, and weight increment circuits for a high density, temperature-compensated analog VLSI neural network are introduced. The synapse circuit, which consumes 4500 /spl mu/m/sup 2/ in a 2-/spl mu/m technology, uses hybrid dynamic and non-volatile weight storage. Dynamic memory allows fast learning while non-volatile memory allows reliable long-term storage and low power dissipation. Measured test results for the synapse are presented. The synapse includes a weight increment circuit that adds offset of only 1 part in 16 bits, thus allowing analog-domain on-chip learning using a weight perturbation algorithm. Simple bias circuits cancel temperature dependent parameters in the synapse-neuron transfer function, allowing reliable operation in the temperature range -55 C to 125 C.>

Article Generation of performance sensitivities for analog cell layout Share on Authors: George Gad-El-Karim North Carolina State University, Raleigh, NC North Carolina State University, Raleigh, NCView Profile , Ronald S. Gyurcsik North Carolina State University, Raleigh, NC North Carolina State University, Raleigh, NCView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 500–505https://doi.org/10.1145/127601.127720Online:01 June 1991Publication History 5citation138DownloadsMetricsTotal Citations5Total Downloads138Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

This paper describes an algorithm that uses dynamic programming to order IC tests so that faulty circuits are detected early in the test sequence and the average test time is minimized.An accurate estimate of the probabilities of individual tests failing, and the joint probabilities of several tests failing is required.These probabilities can be estimated using statistical simulation techniquesor from actual circuits.The ordering algorithm is 0( Tnn2") where n is the number of tests to be ordered, and m is the number of data points.

The effects of radiation exposure on the performance of CMOS integrated circuits are difficult to predict and to simulate due to the bias-dependent device parameter shifts. Simulation methodologies for identification of failure mechanisms and performance estimation are developed. These simulation algorithms are implemented in the PARA simulator for switch-level simulation of radiation effects. Simulation results for test circuits are presented that prove that accurate estimations are possible without CPU-intensive simulation programs.>