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Joseph Arul

dblp:51/4000 · DBLP profile ↗
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5ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-authorComputer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Storage systems · 45% Distributed systems · 30% Processor architecture and microarchitecture · 22%
Computer networks
1 paper
Cellular and mobile networks · 87% Physical-layer communications · 13%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 10 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › i/o architecture › i/o subsystem
disk i/o
0.112006
Using File Grouping to Improve the Disk Performance (Extended Abstract) · HPDC 2006
Storage systems
file systems
0.112006
Using File Grouping to Improve the Disk Performance (Extended Abstract) · HPDC 2006
Cellular and mobile networks › mobility management
Mobile IP
0.012003
An Efficient Fault-Tolerant Approach for Mobile IP in Wireless Systems · IEEE Trans. Mob. Comput. 2003
Cellular and mobile networks
mobility management
0.012003
An Efficient Fault-Tolerant Approach for Mobile IP in Wireless Systems · IEEE Trans. Mob. Comput. 2003
Distributed systems › fault tolerance
failure recovery
0.012003
An Efficient Fault-Tolerant Approach for Mobile IP in Wireless Systems · IEEE Trans. Mob. Comput. 2003
Distributed systems
fault tolerance
0.012003
An Efficient Fault-Tolerant Approach for Mobile IP in Wireless Systems · IEEE Trans. Mob. Comput. 2003
Processor architecture and microarchitecture
instruction-level parallelism
0.012001
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation · IEEE Trans. Computers 2001
Processor architecture and microarchitecture
multithreading
0.012001
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation · IEEE Trans. Computers 2001
Physical-layer communications
wireless communication systems
0.012003
An Efficient Fault-Tolerant Approach for Mobile IP in Wireless Systems · IEEE Trans. Mob. Comput. 2003
Performance modeling and evaluation
simulation
0.012001
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation · IEEE Trans. Computers 2001

Methods — techniques the papers use, named apart from their topics

program-based grouping · 0.1queuing model · 0.1m/g/c/c · 0.1performance simulation · 0.0
YearPublicationVenuePosition
2010 An Efficient Non-blocking Multithreaded Embedded System
Joseph Arul, Tsung-Yun Chen, Guan-Jie Hwang, Hua-Yuan Chung, Fu-Jiun Lin, You-Jen Lee
ICA3PP (1)1
2006 Using File Grouping to Improve the Disk Performance (Extended Abstract)
abstract
As the speed gap between CPU and the secondary storage device will not be narrowing in the foreseeable future, file grouping can be a promising way to reduce the disk I/O latency. The order of sequential access among files observed during the execution of individual programs is very predictable. Based on this idea, we propose a new file grouping model called program-based grouping (PBG). Through the Reiser file system, we implemented PBG into Linux kernel. The experiments demonstrate that PBG out performs both ReiserFS and Ext3. Compared with ReiserFS, PBG can improve the ReiserFS performance by up to 66%
Tsozen Yeh, Joseph Arul, Jia-Shian Wu, I-Fan Chen, Kuo-Hsin Tan
HPDC2
2005 Design and Multithreading Implementation of the Wave-Front Algorithm for Constructing Voronoi Diagrams
Grace J. Hwang, Joseph Arul, Eric Lin, Chung-Yun Hung
ICA3PP2
2003 An Efficient Fault-Tolerant Approach for Mobile IP in Wireless Systems
abstract
This paper presents the fault tolerance of Mobile IP in wireless systems. Mobile IP can support wireless users with continuous network connections while changing locations. It is achieved by allocating a number of mobility agents (foreign agents and home agents) in the architecture of a wireless system. If a failure occurs in a mobility agent, the wireless users located in the coverage area of the faulty mobility agent will lose their network connections. To tolerate the failures of mobility agents, this paper proposes an efficient approach to maintaining the network connections of wireless users without being affected by the failures. Once detecting a failure in a mobility agent, failure-free mobility agents are dynamically selected to be organized as a backup set to take over the faulty mobility agent. Compared to the previous approaches, the proposed approach does not take any actions against failures during the failure-free period. Besides, the hardware redundancy technique is also not used in the proposed approach. The overhead of the proposed approach is analyzed using the M/G/c/c queuing model. The results show that the proposed approach can effectively resolve the fault-tolerant problem of Mobile IP in wireless systems.
Jenn-Wei Lin, Joseph Arul
IEEE Trans. Mob. Comput.2
2001 Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation
abstract
In this paper, the scheduled dataflow (SDF) architecture-a decoupled memory/execution, multithreaded architecture using nonblocking threads-is presented in detail and evaluated against superscalar architecture. Recent focus in the field of new processor architectures is mainly on VLIW (e.g., IA-64), superscalar, and superspeculative designs. This trend allows for better performance, but at the expense of increased hardware complexity and, possibly, higher power expenditures resulting from dynamic instruction scheduling. Our research deviates from this trend by exploring a simpler, yet powerful execution paradigm that is based on dataflow and multithreading. A program is partitioned into nonblocking execution threads. In addition, all memory accesses are decoupled from the thread's execution. Data is preloaded into the thread's context (registers) and all results are poststored after the completion of the thread's execution. While multithreading and decoupling are possible with control-flow architectures, SDF makes it easier to coordinate the memory accesses and execution of a thread, as well as eliminate unnecessary dependencies among instructions. We have compared the execution cycles required for programs on SDF with the execution cycles required by programs on SimpleScalar (a superscalar simulator) by considering the essential aspects of these architectures in order to have a fair comparison. The results show that SDF architecture can outperform the superscalar. SDF performance scales better with the number of functional units and allows for a good exploitation of Thread Level Parallelism (TLP) and available chip area.
Krishna M. Kavi, Roberto Giorgi, Joseph Arul
IEEE Trans. Computers3