A novel thresholding technique is presented for digital channelized receiver to minimize second signal false alarm. The additional constraint placed for signal detection improves the false alarm rate with minimal hardware increase due to the simplicity of the proposed algorithm. Preliminary dual-tone signal analysis with instantaneous dynamic range (IDR) from -12 to -20 dB shows favorable second signal detection rates with no false alarms reported based on 53760 samples per test. The implemented digital receiver samples at 2.048 GHz on Xilinx Virtex 4 field programmable gate array (FPGA) with output throughput rate of 62.5 ns. Exhaustive evaluation of fifty-eight 16 MHz channels includes signals not centered on the frequency bin, which also shows favorable detection results.

A real-time architecture to the Hilbert transform is presented for an implemented digital instantaneous frequency measurement (IFM) receiver to avoid the suspension of data acquisition during signal processing due to input buffer constraints. The ability to continuously process incoming signals allows constant monitoring of the spectrum under interest, which is critical for radar signal tracking. Architectural improvements yield a 99.5% reduction in the amount of hardware used for storage and processing for the Hilbert transform component alone. Data throughput rate of the Hilbert transform increased by a factor of eighty from a single bitstream at 32 mega bits per second (Mbps) to eight bitstreams at 320 Mbps each. The maximum combined throughput rate possible of all eight channels after place and route is estimated at 4264 Mbps and verified for 3200 Mbps. Prior to the modifications, the digital IFM is capable of classifying continuous or short pulse wave signal of 1.2 GHz bandwidth with a major frequency detection error within 2 MHz for every 100 nsec 95.92% of the time.

A previous paper by Wei and Thompson (1990) defined a family of adders based on a modular design and presented an excellent systematic method of implementing a VLSI parallel adder using three types of component cells designed in static CMOS. Their approach to the adder design was based on the optimization of a formulated dynamic programming problem with respect to area and time. The authors first explicitly demonstrate the optimal 32-bit fast carry generator, described by Wei and Thompson, is incorrect. With suitable corrections, a correct 32-bit fast carry generator design is then presented. Next, BiCMOS technology is applied to implement the subcircuit of fast carry generator to accelerate the critical path. The authors show that the critical path delay of 16-bit, 32-bit and 66-bit adders is respectively shortened to 83.89%, 86.89% and 90.62% after introducing the BiCMOS drivers.>

Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In this paper, we present an efficient unified procedure, named three-phase cluster partitioning, to automatically synthesize a pseudo-exhaustive test generator for VLSI BIST design. Previous approaches to the problem of test generation have optimized computational efficiency at the expense of the required hardware overhead, or vice versa. Our design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive test. Based on three-phase cluster partitioning, a design generator named BISTSYN has been developed and implemented to facilitate the BIST design. The input to the design generator is a circuit description at the gate level which is viewed as a netlist. BISTSYN provides the BIST mechanisms as the output. For those conventional circuits which are extremely unsuitable for pseudo-exhaustive test, BISTSYN employs a circuit partitioning tool, named Autonomous, to partition the combinational portion of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. We demonstrate the effectiveness of BISTSYN by applying the method to different examples and practical VLSI designs. The detailed comparisons of our benchmark simulation results against those that would be obtained by existing techniques are also presented.>

Built-In Self-Test (BIST) has been proposed as a powerful solution to VLSI testing problem and pseudo-exhaustive test is a BIST design methodology that provides effective, 100% fault coverage for all testable stuck-at faults. A circuit partitioning method is presented to partition the digital combinational portions of a circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. Furthermore, a tight lower bound on the number of interconnections between distinct subcircuits is derived. These interconnections are required for self-testing each subcircuit when the circuit is partitioned into a specified number of groups of specified sizes. We demonstrate the effectiveness of partitioning method by illustrations of applying the method to circuit examples, benchmark circuits and practical VLSI designs.

Concurrent testing is used to reduce overall self-testing time and further exploit the power of the built-in self-test (BIST) technique. A unifying procedure, called the implicit tree search algorithm (ITSA), is used to fully exploit the test parallelism so that both the total testing time and test resources are optimized. The operation of the ITSA is demonstrated by detailed examples.>

A network partitioning tool, named Autonomous, is presented for partitioning digital combinational portions of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. A built-in self-test (BIST) design generators, named BISTSYN has been developed and implemented to facilitate the BIST design with this partitioning methodology. The experimental results show that Autonomous, when used with BISTSYN on a set of benchmark examples, is feasible for very large designs, and the number of undetected faults is significantly reduced after the circuit is partitioned.>

ModemVLSI circuits with extensive built-in self-test (JUST) resources have the problem of long testing time if the testing for the different parts of the circuits are executed successively.Herein, we present a heuristic solution, called Weighted Cluster Partitwning (WCP), to the problem of long testing time for VLSI circuits.Some of the techniques in current use exploit parallelism in testing VLSI circuits, but the computation is quite expensive.Our solution is a more efficient and effective procedure which explores the space of concurrent test schedule and leads to a considerable reduction of testing time by suitable incorporation of BIST in the circuit.

The author presents a unifying procedure, called three phase cluster partitioning (TPCP), for automated synthesis of a pseudo-exhaustive test generator for built-in self-test (BIST) design. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive testing. A design generator named BISTSYN, based on the TPCP algorithm, was developed and implemented to facilitate the BIST design with this methodology. The input to the design generator can be a circuit description at the gate level which is viewed as a netlist or the circuit output functional dependency sets. BISTSYN provides the BIST mechanisms as the output. The hierarchical design procedure is computationally efficient and produces test generation circuitry with lower hardware overhead and fewer pseudo-exhaustive test patterns than existing techniques.>

At present, there is no efficient synthesis approach for multiport memory synthesis in data path design and only single port memory is considered for register allocation in most synthesis systems. An efficient method, partitioned dependence matrix (PDM), is presented to explore the design space for multiport memory synthesis in which the maximum number of read ports can be same as or different from the maximum number of write ports according to the design constraints. The design generator based on the PDM method was developed and implemented to facilitate the register transfer (RT) level synthesis. The input to the design generator is a behavioral description at the RT level which is viewed as a code sequence. PDM provides the memory mechanism as the output.>

In the built-in self-test (BIST) methodology, the two major problems which must be addressed are test generation and response analysis. An efficient, unified solution to the problem of test generation is presented. A design procedure that is computationally efficient and produces test generation circuitry with low hardware overhead is proposed. The effectiveness of this approach is demonstrated by detailed comparisons of its results with those that would be obtained by existing techniques.>