3D stacked memory enables more off-chip DDR memories. Redesigning existing IPs to exploit the increased memory parallelism will be prohibitively costly. In our work, we propose a practical approach to exploit the increased bandwidth and reduced latency of multiple off-chip DDR memories while reusing existing IPs without modification. The proposed approach is based on two new concepts: transaction id renaming and distributed soft arbitration. We present two on-chip network components, request parallelizer and read data serializer, to realize the concepts. Experiments with synthetic test cases and an industrial strength DTV SoC design show that the proposed approach gives significant improvements in total execution cycle (21.6%) and average memory access latency (31.6%) in the DTV case with a small area overhead (30.1% in the on-chip network, and less than 1.4% in the entire chip).

3D stacked memory is being adopted as a promising solution to offer high bandwidth and low latency in memory access. Compared with the on-chip network design with conventional off chip memory, it gives a new problem of minimizing communication conflicts since multiple concurrent high bandwidth data transfers will flow through the on-chip network. In order to tackle this problem, we propose applying an open-loop flow control scheme based on the accurate global information (destination and status) of on-chip communication. The proposed open-loop flow control scheme exploits the information and selectively buffers and arbitrates data transfers to remove conflicts at destinations in a preventive manner. As an implementation of the presented scheme, we present on-chip buffers called Buf3D's that share the global information with each other to perform the selective buffering and arbitration of data transfers. Experiments with synthetic test cases and an industrial strength DTV design show that the proposed method improves aggregate memory bandwidth significantly (average 19.0 %~25.8 % in the synthetic cases and up to 18.4 % in the DTV case) with a small area overhead (15.2 % in the DTV case) of on-chip network.

An important issue in register-transfer-level (RTL) hardware verification is the ability to check specified functions and to determine the presence of an error. Code-level coverage is often used to measure the success in verification at this level. However existing code-level coverage inaccurately estimates the verification result by considering only the excitations of functional blocks. While it may be impossible to achieve 100% correctness with code-coverage measure, checking excitation of functions and monitoring the effects at output ports can improve reliability of functional verification. This paper presents an RTL functional verification approach that evaluates the excitation-states of conditional expressions and propagates the excited information to output ports. The proposed approach with Verilog PLI-based implementation provide more meaningful coverage value that can measure the extent of functional verification in a very effective way during logic simulation.

A system-level verification framework is presented that combines the speed of hard-wired (FPGA-based) emulation and the observability of gate-level simulation. A checkpoint approach is developed for (1) periodic capturing of the machine state from an emulation, (2) sampling of the emulation output for error detection, and (3) constructing a piece-wise simulation run, necessary to debug the design in an event of an error detection from the emulation. The checkpoint frequency is optimized to reduce the cost of downloading the state data during a hardware emulation. A sampling of the emulation output also minimizes the network-bandwidth and storage-space requirements associated with instrumenting for error detection.