Two test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-bit random access memory. In both strategies the data-in line is randomly driven. One of the two strategies uses random selection of both the address lines and the read/write control. The other strategy sequentially cycles through the address space with deterministic setting of the read/write control. The relative merit of the two strategies is measured by the average number of accesses per address needed to meet a standard test quality level.>

Five test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-b random-access memory. In all five test strategies the data-in line is randomly driven. Three of five strategies use random selection of both the address lines and the read/write control. The other two strategies sequentially cycle through the address space with deterministic setting of the read/write control. The relative merit of these five strategies is measured by the average number of accesses per address needed to meet a standard test quality level. It is concluded that ETWO (explicit memory test with word operations) offers the best performance and is quite easy to implement.>

An analytical method is described for determining the random pattern testability of permanent faults in the prelogic driving the data-in and the address lines of a multiport random access memory whose outputs are directly observable. The results can be used with minimal extensions to existing detection probability tools such as the cutting algorithm.