When Instant Messaging (IM) users experience delays in receiving responses from a partner, they may interpret these delays in a variety of ways (e.g., a technological problem vs. the partner is avoiding interaction), and these interpretations can have social consequences. In a laboratory study, we explored whether the presence of a typing indicator shaped people's interpretation of delays. Participants collaborated with a confederate on a time-sensitive task and retrospectively reviewed their interaction. We manipulated delay condition (none, delay, delay with typing indicator) and time pressure (low, high). Participants rated their partners as significantly lower in conversational involvement, were more frustrated, and liked their partners less during a delay whether or not they saw a typing indicator. We discuss implications for the design of new features for IM clients that help people interpret delays appropriately.

When people communicate, their messages convey affect alongside informational content. The affective dimension of messages is often unclear and open to multiple interpretations especially in an intercultural context. Thus, interlocutors may or may not achieve a state of affective grounding in which each person's affective behaviors are correctly interpreted by his/her partners. The current study examines the effects of culture on affective grounding. We conducted a laboratory experiment in which pairs of participants, half from America (A) and half from China (C), collaborated over instant messaging (IM). We found that affective grounding was harder to achieve for AA and AC pairs, but easier for CC pairs. We propose several design solutions to facilitate affective grounding in remote collaborations.

The authors propose a new approach for synthesizing the dynamically configured pipelines supporting variable data initiation intervals (DIIs). Compared to the previous research where the pipeline synthesis is confined to those with fixed DIIs, the proposed system allows powerful design space exploration by removing the constraints of fixed DIIs. The proposed algorithm tries to optimize the area of pipeline structures by fully utilizing hardware resources to which abstract operations in high-level design descriptions are assigned, while meeting the given timing constraints in the clock cycle time, number of stages, and data initiation sequence. Experimental results on benchmarks show that new design points, efficient in speed and in area, can be found by removing the restriction of fixed DIIs in the synthesis of pipeline structures.

In this paper, we propose a novel algorithm for synthesizing the pipeline structures with variable data initiation intervals (DIIs).Compared to previous researches where the pipeline synthesis is confined to those with fixed DIIs, the proposed algorithm tries to optimize the pipeline latency by fully utilizing hardware resources to which abstract operations in high-level design descriptions are assigned.supported in those systems is confined to the pipeline structures with fixed DII (Data Initiation Interval).Pipeline structures with fixed DII have been widely employed for their simplicity of control and design.Pipeline structures with variable DIIs are the generalized form.It is well known that the high throughput can be obtained with variable DIIs.However, the complexity of the synthesis algorithm and pipeline control prevent the pipeline structures with variable DIIs from being utilized in digital system design.By automating the design of pipeline structures with variable DIIs, we can obtain hardware designs with higherperformance in throughput.In this paper, we propose novel algorithms for synthesizing the pipeline structures with variable DIIs.In Section 2, pipelining concepts are described.Scheduling, module allocation for pipeline structures with variable DIIs are presented in Section 3. Section 4 presents the experimental results for benchmarks and conclusions are drawn in Section 5.Determining time-overlapping of pipeline stages, the proposed algorithm performs scheduling and module allocation using the time-overlapping information for the proper control of pipelines with variable DIIs.Experimental results on benchmarks show that significant improvement can be achieved both in speed and in area.

Hermod is an interactive behavioral synthesis program developed at Stanford University. With the use of a combined control and data flow graph (C /DFG) as an intermediate representation, Hermod generates functional blocks and their interconnection from behavioral descriptions. Hermod supports a menu-driven interface, displaying the control and data flow graph with a set of legitimate timing-cuts and its hardware representation. Emphasizing user participation, the system allows the user to control state partitioning and resource sharing through a graphical interface to explore the maximal design space. Written in an object-oriented language C ++, Hermod generates a hardware representation in several minutes from a behavioral description of practical size on a VAXstation II /GPX.

In an effort to speed up simulation, a novel algorithm,, called incremental simulation evaluates the circuit components that can be affected directly or indirectly by design changes, utilizing the information generated during the previous simulation to reduce the number of component evaluations to a minimum. The authors describe the design and implementation of the incremental algorithm for logic or functional simulation, which substantially improves the run-time performance over existing simulators by using the incremental property of the hardware design process.>

In this paper we propose a new algorithm for optimal PLA folding based on a graph theoretic formulation. An efficient best-first search (BFS) algorithm is presented which finds a near-optimal PLA folding. The proposed algorithm first constructs the longest paths on the associated disjoint graph generated from the PLA personality matrix, and then extracts the ordered folding sets from the constructed paths. The algorithm is shown to be effective for most test cases.