John Watkins

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3ranked-venue papers

1as first author

0since 2021 · last 2013

0009-0005-7864-648XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 61% Integrated circuit design · 39%

Topics — the 4 heaviest of 4, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Electronic design automation › logic synthesis › decision diagrams binary decision diagram	0.2	1	2013	Combinational Logic Design Using Six-Terminal NEM Relays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Integrated circuit design digital circuit design	0.2	1	2013	Combinational Logic Design Using Six-Terminal NEM Relays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Electronic design automation logic synthesis	0.2	1	2013	Combinational Logic Design Using Six-Terminal NEM Relays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Integrated circuit design low-power circuit design	0.0	1	2013	Combinational Logic Design Using Six-Terminal NEM Relays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013

Methods — techniques the papers use, named apart from their topics

binary decision diagram · 0.2

Year	Publication	Venue	Position
2013	Combinational Logic Design Using Six-Terminal NEM Relays abstract This paper presents techniques for designing nanoelectromechanical relay-based logic circuits using six-terminal relays that behave as universal logic gates. With proper biasing, a compact 2-to-1 multiplexer can be implemented using a single six-terminal relay. Arbitrary combinational logic functions can then be implemented using well-known binary decision diagram (BDD) techniques. Compared to a CMOS-style implementation using four-terminal relays, the BDD-based implementation can result in lower area without major impact on performance metrics such as delay, and energy (when the relays are scaled to small dimensions). Although it is possible to implement any combinational circuit with a single mechanical delay, the relay count can be significantly reduced for complex logic functions by allowing multiple mechanical delays. Daesung Lee 0002, W. Scott Lee, Chen Chen 0018, Farzan Fallah, J. Provine, Soogine Chong, John Watkins, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	7
1993	An Integrated Environment for Concurrent Development of a Pixel Processor ASIC and Application Software abstract The paper describes a unique environment for concurrent software and hardware development of a memory controller ASIC containing an embedded graphics pixel processor. The center of this customized environment is a behavioral simulator which is used for both hardware verification and software development. The software and hardware are developed concurrently. The behavioral simulator enforces consistent agreement between software expectation and hardware functionality.> Raymond Roth, John Watkins, Michael Hsieh, William Radke, Donald Hejna, Richard Tom, Byung Kim	ICCD	2
1993	A Memory Controller with an Integrated Graphics Processor abstract The paper describes the SX graphics accelerator. It is a programmable processor built into a workstation memory system. The goal of the SX is to achieve performance comparable to that of low end 2D and 3D graphics processors and to surpass low end imaging performance, at the lowest possible cost. The SX contains an integer vector processor, with an instruction set tailored to the needs of image processing and multimedia as well as 2D and 3D graphics. It can directly access data in both video and main memory, allowing accelerated processing on images up to 512 Mbyte in size. The SX offers a cost-effective method of providing a rich graphics and image processing capability compared to traditional workstation and accelerator approaches.> John Watkins, Raymond Roth, Michael Hsieh, William Radke, Donald Hejna, Byung Kim, Richard Tom	ICCD	1