A low Specific Absorption Rate (SAR) antenna with enhanced radiation efficiency and improved gain is proposed for further improvement of long-range biological monitoring systems within IoMT platforms. A unidirectional uniform current distribution form with high radiation efficiency and low SAR values was first theoretically calculated and proved, which is the current distribution with a ratio coefficient N. Subsequently, we achieved the desired current distribution by ingeniously utilizing the higher-order mode currents of the meandering dipole. The simulation current distribution in each section of this third-order mode dipole agrees with the theoretical calculations. The antenna operation frequency covers the ISM 2.45 GHz band (2.4-2.48 GHz), and the antenna has a peak SAR of 155.5 and 59.2 W/kg for 1-g and 10-g of tissue, respectively. The measured radiation efficiency is more than 2.4% in the band, the peak efficiency is more than 3%, the gain is more than -10.27 dBi in the band, and the peak gain is -8.53 dBi. In addition, based on the communication link budget analysis, it can be confirmed that the proposed antenna can establish a reliable communication link up to distances of 15 m (78 Mb/s) and 20 m (10 Mb/s) at 2.45 GHz, for transferring high data rate information.

This paper presents a fully integrated NMOS stimulator using a hybrid dynamic bulk biasing technique (HDBT) and a charge-pump-like control technique (CCT) in a 180-nm bulk CMOS technology. HDBT integrates terminal-voltage-dependent and logic dynamic bulk biasing to set the bulk bias voltage according to the electrode voltage. CCT adds a DC voltage to the gate terminal through a diode and capacitor to help turn on the NMOS transistor. It helps turn off the transistor by shorting the source and gate terminals together and applying two diodes across the drain and source terminals. To achieve an electrode voltage higher than the breakdown voltage of substrate diode ($V_{\mathrm {BD}}$) with an independent power supply, a high voltage tolerant switch is proposed with HDBT and CCT. A high voltage interface is also proposed, utilizing the capacitor adaptive biasing, to overcome the limitation of$V_{\mathrm {BD}}$between the high and low voltage domains and to accommodate the variation of electrode voltage. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves a maximum electrode voltage ($V_{\mathrm {E,MAX}}$) of 18.74V under a 3.3-V supply, with a highest$V_{\mathrm {E,MAX}}$/$V_{\mathrm {BD}}$ratio of 1.27 than state-of-the-art stimulators, including non-standard technology designs. In a continuous output test mode over 10million cycles, the variation of$V_{\mathrm {E,MAX}}$is less than 150mV. The measured maximum residual voltage on the capacitor is 13.55mV.

This paper presents a compact, reconfigurable dual-band bidirectional image rejection mixer for 5G FR2 applications. This mixer uses a current-flipping bidirectional mixer to achieve bidirectional signal transmission and up/down conversion. A reconfigurable and tunable poly-phase filter (PPF) is used for sideband selection and calibration. It uses a miniaturized passive LO quadrature generation network (QGN) for high-precision quadrature signals. Simulated in 40-nm CMOS, the mixer operates from 24-29.5 and 37-43.5 GHz with an LO frequency of 30-37 GHz, making the upper and lower sidebands mirror images of each other. The IF range is 2.5-6.5 GHz. Post-simulation results show that in both RX and TX modes, the peak conversion gain (CG) is -6.6 dB and -6.2 dB, respectively, with image rejection ratio greater than 39 dB. The simulated LO-to-RF and LO-to-IF isolation is better than 57 and 69 dBc. The chip core area is only 0.63 × 0.83 mm2.

This paper presents a hybrid all-NMOS rectifier with two gate-biasing techniques to extend the power dynamic range (PDR) for wireless power transfer. The proposed hybrid rectifier combines the strengths of the cross-connected (CC) and diode-based (DB) configurations, achieving both a high forward current and a small reverse current along the PDR. Additionally, two separate gate-biasing techniques are employed to optimize the gate bias voltage for the gate-biased-CC and gate-biased-DB parts, respectively. All transistors in the rectifier are NMOS transistors, which can minimize the total area when extended to multi-stage configurations. The circuit is implemented in a 180-nm CMOS process, occupying an area of 0.195 mm2. Experimental results show a sensitivity of -10.3 dBm with a 1 MΩ load and a peak power conversion efficiency of 78.6% at -7.4 dBm with a 3 kΩ load. In addition, the proposed rectifier achieves a PDR greater than 22.3 dB with loads below 5 kΩ.

This article proposes a comprehensive calculation method for determining the radiation pattern of a conformal circularly polarized antenna array, which is increasingly utilized in advanced communication systems for IoT applications due to its ability to conform to various surface geometries and maintain consistent polarization. The method involves defining the positions of antenna elements on a conformal surface using spherical coordinates, calculating the individual element radiation patterns for circular polarization, and deriving the array factor that accounts for the spatial arrangement and phase excitation of the elements. On this basis, an antenna array with continuously adjustable half-power beamwidth (HPBW) and axial-ratio beamwidth (ARBW) is designed. The method is validated through simulation of the array, demonstrating its capability to accurately predict the radiation characteristics and reveal the impact of conformal geometry on performance. Measured results are consistent with the simulated results, verifying the proposed method’s validity. The obtained HPBW is 198o of the designed array and can be continuously adjusted from 34∘-232∘, and the gain is 12.2 dBi at the range of 2.4-14.6 dBi at the centre frequency of 2.45 GHz. This calculation method provides a robust framework for future research and development in conformal antenna technology.

An oscillator-based reconfigurable modulator is proposed to support multi-mode and fast modulation. A direct-modulation structure composed of the cross-coupled oscillator with the fast-switched film bulk acoustic resonator (FBAR) is used to enhance the frequency stability under fast OOK/BFSK modulation. To avoid extra phase-reversal circuitry, a polarity-swapped switching structure is employed in the differential branches of the modulator to achieve energy-efficient BPSK modulation, and this structure is also reused as a buffer stage for OOK/BFSK modulation to avoid the loading effect. In addition, an adaptive fast-switching technique is also proposed to improve OOK/BFSK modulation data rate and energy efficiency. The modulator is fabricated in a 180 nm CMOS technology. The free-running oscillation frequencies with two FBARs are 962 MHz and 990 MHz, and the measured phase noises are -137.3 dBc/Hz@1MHz and -137.1 dBc/Hz@1MHz, respectively. For OOK/BFSK/BPSK modulation, the proposed modulator demonstrated 280/325/67.6 pJ/bit energy efficiency and 5.63/4.20/5.55 % rms EVM with 10/10/50 Mbps data rates.

This paper presents a fully integrated stimulator using a dynamic bulk biasing technique and a dynamic control scheme in a 180-nm bulk CMOS technology. Unlike the conventional bulk biasing method, the bulk bias voltage is dynamically set according to the different stimulation phases. It avoids the underlying leakage current paths, and improves the maximum stimulation voltage compliance (MSVC). Together with dynamic bulk biasing scheme, a high voltage interface is designed to overcome the limitation of the breakdown voltage of the substrate diode ( V$_{\mathbf{BD}}$) between the high and low voltage domains. An all-NMOS dynamic charge pump is also proposed as a dynamic power supply above V$_{\mathbf{BD}}$and provides dynamic bulk-biasing voltages. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves an MSVC of$\pm$16.5 V under a 3.3-V supply, and the achieved MSVC is$\sim$1.11 times higher than the V$_{\mathbf{BD}}$($\sim$14.8 V) of the substrate diode. The stimulator is also measured in a continuous output test mode for over 10 million cycles, the variation of$\vert$MSVC$\vert$is less than 200 mV.

This paper presents an ultra-low power 802.11ba receiver for Internet of things (IoT) devices. A low-power third-harmonic mixer based on a 6-phase non-overlap local oscillator (LO) operating at 1/3 RF frequency is proposed to improve the out-of-band rejection. The analog finite-impulse-response (AFIR) filter in the baseband is designed for better adjacent channel rejection (ACR) while maintaining the low power consumption. A tunable tapped-capacitor resonator is designed to provide the passive voltage gain and input matching with zero power consumption. The simulation results show that the proposed receiver achieves a sensitivity of -93.5 dBm with the conversion gain of 51 dB. It can achieve$\leq-\mathbf{15}\mathbf{dB} \ \text{S}_{11}$at different process corners via frequency tuning. The simulated ACR is ~93 dB for 802.11ba standard. The receiver consumes a total power of$\mathbf{197}\ \boldsymbol{\mu} \mathbf{W}$, and the core area is 0.25 mm2.

In this paper, a high global efficiency OOK transmitter (TX) working at 400–460 MHz is proposed by utilizing third-harmonic edge-combining technique for low power biomedical applications. The operation frequency of the proposed TX before the third-harmonic edge-combiner (THEC) is 1/15 of the output RF frequency and 1/3 of the traditional edge-combiner-based TX. The multi-phase signals used for edge combiner (EC) are generated by a delay-locked loop (DLL) at a relative low frequency, which significantly reduces the overall TX power consumption. The TX is designed in 55-nm CMOS process with a core area of 0.02 mm2, the proposed TX consumes a DC power of$98.75\ \mu\mathrm{W}$under a 0.8 V supply voltage. The simulated output power is −14 dBm with 20 Mbps OOK data. The TX achieves a 41% global efficiency and a 4.94 pJ/bit energy efficiency, respectively.

A Ku-band low-phase noise oscillator, using a weakly coupled cavities resonator (WCCR), is proposed based on substrate-integrated suspended line (SISL) technology. Different from using a bandpass filter as the frequency selector for the feedback oscillator, we use weak coupling between resonators to form a resonator with a higher$Q$. The theoretical analysis of weak coupling is derived. Under weak coupling, the equivalent$Q$and insertion loss of the WCCR is given based on the mathematical deduction. The proposed WCCR can double the$Q$factor of the single cavity resonator (SCR) at the expense of an increase in the insertion loss. Two oscillators using WCCR and SCR are designed and fabricated to verify the theoretical analysis. The measured results show that the loaded$Q$of WCCR increases by 80% compared with the SCR. The proposed oscillator has a low measured phase noise of −137.36 dBc/Hz at 1 MHz offset from the carrier frequency of 12.355 GHz, and the FOM is −207.12 dBc/Hz. Compared with the oscillator using SCR, the measured phase noise is improved by 5.13 dB. Moreover, the proposed oscillator based on SISL technology has the advantages of low cost, compact size, and self-packaging properties.

Multimode resonators (MMRs) can be utilized to build multiband bandpass filters (MBPFs). Each individual mode serves as the operating mode for one of the passbands in a well-known coupling topology. However, several difficulties are involved with the classical design method. In this article, we present a novel star-like topology to design MBPFs based on MMRs. Differently from the classical use, in the proposed novel topology, they are so regarded as bandstop resonators and provide multiple controllable transmission zeros. To explain the proposed concept and the implementation method, two bandstop MMRs – a classical dual-mode stub loaded resonator (DSLR) and a new tri-mode dual-stub loaded resonator (TDSR) – are investigated with detailed design formulas and diagrams. Then, a tri-band MBPF with equal individual sub-bands, a quad-band and two quint-band MBPFs with unequal individual sub-bands are synthesized and designed using the proposed bandstop MMRs. Additionally, simulations and experiments are used to verify the efficiency of all prototypes. Good agreements with the theoretical calculations are observed for all the MBPFs.

This paper presents a 21.5-to-36 GHz 6-bit radio-frequency variable gain amplifier (RF-VGA) for the fifth generation (5G) communication phased-arrays in 0.13-$\mu$m SiGe BiCMOS technology. To maintain a wideband stable power gain and accurate gain control under all operation states, the two-stage amplifier comprising a cascode amplifier with RC compensating network and a common emitter amplifier is designed and realized. The measured results reveal a wide gain tuning range of-16 to 16 dB, a gain resolution of 0.5 dB with 6-bit digital control, a minimum RMS gain error of 0.04 dB only, 3-dB bandwidth of 13.5 GHz, output $\mathrm{P}_{\mathrm{ldB}}$ compression point of 9.3 dBm, and total DC power consumption of 23.5 mW under 1. 6V supply. The chip area is 0.64×0.4mm2, excluding the testing pads. To the best of the authors’ knowledge, it achieves the best FOM among similar reported VGAs.

In this paper, a broadband receiver front end for 0.1 to 40 GHz application, fabricated using 0.15-μm GaAs E-mode pHEMT process, is reported. The receiver front end consists of a broadband low-noise amplifier (LNA) and a broadband mixer. To achieve low noise and significant bandwidth extension, a three-stage LNA, cascading one stage cascode amplifier with feedback and bandwidth extension techniques, to two stage cascode Darlington amplifiers with feedback, is proposed. The bandwidth extension principles of LNA are analyzed theoretically and verified experimentally. Measurement results show that the proposed LNA exhibits an average gain of 23.7 dB with ± 1.5-dB variation, a typical noise figure of 3.8 dB, maximum OP1dBof 8.7 dBm in the frequency range from 0.1 to 40 GHz. A symmetric distributed drain mixer (SDDM) is proposed to provide broad bandwidth while ensuring an IP1dBof up to 5.8 dBm. The design procedure of SDDM is presented in detail. Experimental results indicate that the SDDM features a less than 7-dB conversion loss, an IP1dBof up to 5.8 dBm with zero dc dissipation and better than 15-dB isolation of LO-to-RF and IF-to-RF ports from 0.1 to 40 GHz. Finally, the LNA and SDDM are integrated as a 0.1 to 40-GHz receiver front end. Measurements illustrate that the receiver front end shows good matching with better than 10-dB return loss at RF and LO ports, and larger than 15-dB conversion gain in 0.1 to 40-GHz frequency range. The receiver occupies only 1.89-mm2chip area including test pads. To the best of the authors' knowledge, the designed receiver front end has the widest bandwidth among reported receivers fabricated by using GaAs process.

This paper presents the design of a compact 60-GHz phase shifter that provides a 5-bit digital phase control and 360° phase range for beam-forming systems. The phase shifter is designed using the proposed cross-coupled bridged T-type topology and switched-varactor reflective-type topology. The topologies are analyzed using a small-signal equivalent circuit model. Furthermore, the design equations are derived and investigated. To validate the theoretical analysis, 60-GHz 5-bit 360° phase shifters are designed in a commercial 65-nm CMOS technology. The fabricated 360° phase shifter features good performance of 32 phase states from 57 to 64 GHz with an rms phase error of 4.4°, a total insertion loss of 14.3 ± 2 dB, an rms gain error of 0.5 dB, P1dB of better than 9.5 dBm, and the power consumption of almost zero. To the best of our knowledge, the designed 360° phase shifter with the size of 0.094 mm2is the smallest 5-bit passive phase shifter at frequencies around 60 GHz.