In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the ompression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduces the computation time to find a solution for partial LFSR reseeding. Experimental results on ISCAS89 benchmark circuits show that our approach is better than either dictionary coding or LFSR reseeding, and outperforms several test data compression methods proposed recently.

For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this paper we first study the reason for strong correlation between Iddq currents for different test vectors, then build a model to estimate the correlation. Based on this model, we propose three test vector selection methods to improve the fault detection ability of ratio-Iddq testing by selecting test vector pairs with the highest correlation. Hspice simulation showed that the fault detection ability can be improved by as much as an order of magnitude. We also describe a test vector partitioning technique to increase the correlation between Iddq currents of different test vectors.

Dynamic Idd test methods have been shown to detect defects that escape other test techniques. Normal process variations decrease the fault coverage and affect the performance of dynamic Idd test techniques. A dynamic-current based test metric, Energy Consumption Ratio (ECR), has been proposed to address the process variation problem and has been validated through extensive simulations and applications on manufactured circuits. In this paper, we first discuss the problems in practical implementation of ECR tests on large-size circuits of advanced technology, e.g., increased circuit size and leakage current degrade ECR performance. We then propose two possible solutions: one is based on extensive statistical data analysis and another uses an enhanced scan design to partition the circuit. Experimental results from simulations and actual devices are included in this paper.

DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as Cache-Only Memory Architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes the COMA to effectively decrease the gap between modern high-performance microprocessors and the bus. As microprocessors become faster and demand more bandwidth, the already limited scalability of a shared bus decreases even further. DICE tries to optimize the COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the "last memory block" problem on replacement. In this paper, we present a global bus design for a bus-based COMA multiprocessor using the IEEE Futurebus+ standard backplane bus and the Texas Instruments chip-set. Our design demonstrates that necessary bus transactions for DICE can be done efficiently with existing standard bus signals. Considering the benefits of the COMA and the little design complexity it adds to the conventional shared-bus multiprocessor design, a bus-based COMA multiprocessor such as DICE can be become a viable candidate for future shared-bus multiprocessor designs.

Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with (inheriting) the test vector for fault F/sub i/. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that ITPG is very efficient with a small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits.>

Feedback shift registers (FSRs) are sometimes implemented with inversions between stages to improve their testability and their ability to locate faults. These intrainverted FSRs (IFSRs) can be realized with less overhead than standard linear feedback shift registers (LFSRs). It is shown how to relate the cyclic behavior of the LFSR and the corresponding IFSR, based on the same feedback polynomial, so that IFSRs can be designed to exploit the inherent implementation advantages while exhibiting the well-known behavior of LFSRs. In particular, it is shown that the cyclic and serial output behavior of LFSRs can be emulated by IFSRs when loaded with the appropriate initial states for most feedback shift register lengths and feedback polynomials. How the initial state for the IFSR can be derived, given the feedback polynomial and the initial state of the desired cycle in the LFSR, is described. Conditions under which such mapping of behavior cannot be guaranteed are given.>

An approach is proposed to encoding states of sequential circuits that takes advantage of the concept of error detection with latency, and which is applicable to a much broader class of sequential machines. An encoding methodology is introduced that uses tree codes for online detection of sequencing errors with latency in sequential circuits. This approach has the potential to yield designs with less complexity and greater error coverage than schemes based on block codes. The potential benefits this approach are demonstrated, including increased error coverage with simultaneous reductions in circuit complexity.>

The issue of testing two-dimensional iterative arrays with a constant number of test vectors independent of the array size (C-testability) is discussed in this paper. Sufficient conditions for C-testability are stated. It is shown that any two-dimensional array can be modified to become C-testable. An extension to systolic (synchronous) arrays is made. The approach simplifies testing systolic arrays by using one test vector to test many cells of the array in a periodic fashion. A two-dimensional array for matrix multiplication is used to illustrate the approach for systolic arrays.

This paper specifies procedures for defining a monitor circuit that can detect faults in microprogram sequencers. The monitor and the sequencer operate in parallel and errors are detected by comparing outputs from the monitor circuit with outputs from the sequencer. Faults that cause errors in the flow of control are detectable, as well as some faults that cause errors only in the microinstruction fields. The design procedure presented for monitors consists of four parts. First, a model of the program flow is constructed that only retains the information required to define a monitor. Second, faults in a specified fault set are modeled by the errors they cause in the program flow model. Third, the functional requirements of the monitor are specified in terms of partitions on the states of the program flow model. Fourth, the logic design of the monitor is completed.

An analysis for a multiprocessor system with a shared bus is given. The analysis applies to application areas where the task to be performed can be partitioned into largely independent subtasks. Each subtask requires cyclic execution on continuous data input. The objective is to determine the processing power of such a system as the number of subtasks or, equivalently, as the number of processors is increased.

The authors have written an introductory textbook on switching algebra and its application to logic system design. The book contains almost no formal mathematical presentation and, hence, is quite easy to read. The level of the presentation could easily be handled by third-year undergraduate students. (The authors state that the material is suitable for approximately a one-semester course, but do not specify an intended level.) No background in switching algebra is assumed or required. At various points throughout the textbook, some of the practical aspects of logic system design are mentioned and the impractical aspects of the material are pointed out where appropriate. The method of presentation and the orientation will appeal to students with an engineering background, but students with a strong mathematical bent will not be as interested.

A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.

An asynchronous sequential network is an interconnection of several asynchronous sequential circuits. Asynchronous networks are classified according to the relative time delay of the individual circuit's feedback signals and input signals. They are also classified by the manner in which the circuits interact. In addition, another network model uses duplicate paths for the feedback signals and the input signals of a circuit where the duplicate paths have differing delays. The partition theory of Hartmanis and Stearns [5] is used for characterizing some of the network types in a manner analogous to the characterization of synchronous sequential networks. The special case where each circuit in the network has only two states is equivalent to specifying a state assignment for the overall network and this leads to a characterization of some state assignments for asynchronous circuits. In particular, any arbitrary state assignment for the network which has duplicate paths and delays is shown to be free of critical races, and another network model leads to a variation of the minimum transition-time state assignments which in certain cases may require fewer state variables.

The problem of decomposing an asynchronous sequential circuit into the serial connection of two asynchronous sequential circuits is considered. Six types of serial connections are defined, and necessary and sufficient conditions are derived for making five of the six types of serial decomposition, while sufficient conditions are derived for the sixth. Systematic and constructive procedures are presented for making each of the decompositions.