More and more IoT use cases require trustworthy computing from cloud/back-end services, which cannot necessarily provide a fully trusted execution environment, data immutability, and traceability. The integration of IoT with the blockchain technology is one of the most promising solutions to achieve the previously mentioned features in the IoT networks. Researchers are also interested in integration solutions, and several solutions are already present in the scientific literature. However, there are still some uncertainties in establishing a direct and effective interaction between an IoT device and the given blockchain. In this work, we propose the first IoT hardware architecture model designed to accelerate time-consuming operations of IoT-Blockchain. The proposed IoT hardware architecture model is programmed in SystemC-TLM and can provide a significant reduction in execution time, 53% and 18% when running Hyperledger Sawtooth and Ethereum applications, respectively.

Nowadays, Internet of Things applications face serious data and privacy protection vulnerabilities. To address some of the data protection and privacy issues, in this work we propose a new design for the self-encryption method based on a cryptographic-puzzle algorithm, that includes the generation of multiple secret keys, derived from the plaintext. As the ciphertext is constructed from several chunks of encrypted data, the absence of one of the decryption keys or one of the encrypted chunks renders recovery of the original plaintext nearly impossible. As security improvement upon to other related work proposing self-encryption, the plaintext is mixed with random values in order to use a technique known as Privacy Amplification. Privacy Amplification is achieved by applying cryptographic functions from which SHA-2 family is based on. Implementations of our design are also provided, and they are enabled for standalone and back-end execution systems. Furthermore, performance and security results and comparisons with previous related work are also provided. The security analysis confirms the use of the SHA-2 cryptographic hash family for Privacy Amplification.

Private or consortium blockchain networks have fewer verified participants and offer better throughput and transaction efficiency than public networks. However, as more and more blockchain consensuses are designed for private or consortium networks, their performances are often estimated without a practical use case implementation. In our use case, participants do not have to trust each other but still work together to build an ecosystem where users control their data and information. This paper analyzes the performance (transaction throughput, rejections, node participants) of Byzantine Fault Tolerant Consensus (BFT) using two blockchains: Hyperledger Sawtooth and Ethereum.

Bringing artificial intelligence to embedded devices has become a central research topic in many scientific domains (environment, agriculture, sociology, health...). For Human Activity Recognition, Artificial Neural Networks (ANNs) have shown their capability to provide better performance compared to other machine learning methods. However, ANNs suffer from two major limitations. First, ANNs are often trained using supervised learning requiring labelled databases, which are often difficult to build in real applications. Then, those algorithms are usually very expensive in terms of computing power. For that reason, their integration into low-power microcontrollers has been so far only evaluated to a limited extent. In this paper, we propose to evaluate quantitatively and qualitatively the embedded implementation of different neural networks for human activity recognition. First, supervised learning approaches are presented, followed by an exploratory study of unsupervised learning approaches using Self-Organizing Maps. Finally, some aspects of embedded unsupervised online learning are investigated to improve classification results using subject-specific data over a more general training. Each neural network is tested on a Human Activity Recognition dataset acquired from a smartphone using accelerometer and gyroscope sensing information (UCI HAR) and deployed on the SparkFun Edge board. This board hosts a low-power ARM Cortex-M4F-based microcontroller.

Today we find several solutions how to adapt IoT applications on blockchain technology. The most of the IoT devices have limited hardware resources to be able to execute a blockchain applications and take a real part of blockchain as a blockchain node. In this paper we analyzed Ethereum "aleth" blockchain and we identified the most called cryptographic functions that were used during the execution. Our aim is to model a low power consumption IoT architecture that can execute this blockchain application. The given architecture is deployed by a SystemC model and we used dedicated hardware accelerators to increase the performance. In addition we would like to deploy an architecture that meets the requirements of our industrial partner Renault. Renault figured out with a new type of use case with blockchain and especially with Smart Contracts applications where every cars are connected on a blockchain. With our IoT device model we could obtain a high gain of performance.

Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows at transactional level are missing. In this paper we describe how a power/clock intent could be described at transactional level using a separation of concerns process and how the transactional simulation code merging functional and power behaviors can be generated automatically using a model-driven engineering approach.

The paper focuses on techniques for the verification of software implementing communication functionality in networked embedded systems. We discuss the merits and limitations of tools for the simulation of a networked embedded system executing the binary code of the network protocol stack. In particular, we compare different solutions to extend a virtual platform to simulate the node of interest in a realistic communication scenario involving different network nodes. We then explain how this solution has the potentiality to perform verification of the protocol stack, which would be a great asset for industry and academia to validate the communication software under development or use.

Due to the ever-increasing demands on energy efficiency, designers are struggling to construct efficient and correct power management strategies for complex System-on- Chips (SoCs). The validation of an efficient power intent for a SoC is challenging and should be considered at early stage of the electronic system-level (ESL) design flow. To tackle this issue, we propose a high-level modeling approach on top of SystemC/TLM standard allowing the control structure of a power intent to be described in relationship with a functional transaction-level model (TLM) of a SoC. We consider a separation of concern approach in order to make easier the exploration of power intents and the optimization of power consumption. In this paper, the focus is set on an abstract clock intent model through a generic library and a modeling methodology allowing the development of a power management strategy on top of a functional SystemC-TLM model of a virtual prototype. A case study is used to demonstrate by simulation experiments the efficiency of this approach illustrating its capability to analyze effects of power management on performance and power consumption.

In a Reconfigurable System-on-Chip (SoC) platform, the application is divided into threads managed by an operating system, and whereas some threads are implemented as hardware threads and allocated into a partition of the chip, others run as software threads on embedded processing elements. Relying on the Multicore Resource management API (MRAPI) specification and client-server mechanisms, we propose solutions to provide a flexible access to the operating system services for every threads whatever is the core they are running on. In order to improve the application deployment process when targeting HRSoC, we realized both a hardware and a software implementation of this API. Depending on affinities of the operating system services with each core, such a solution allows a fine-grain implementation of these services over the platform.

In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nmof values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to ¿(nmlog2nm). This complexity starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation is quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual simulations.

Patterns, middlewares and frameworks have been used for decades in software architecture to address the main problems encountered today by the MPSoC and NoC communities: heterogeneity of languages, programming models, simulation/execution environments, interaction semantics and communication protocols. A complete semantics mapping of CORBA interface definition language (IDL) and general inter-ORB protocol (GIOP) on the open core protocol (OCP) has been investigated for hardware components. This mapping is generic, highly configurable and illustrated through our target application: software defined radio.

In the scope of initial discussions about a standard OMG IDL-to-VHDL language mapping, we present some requirements and propose a configurable mapping. We demonstrate the advantages of a common component-oriented approach to specify HW and SW interfaces compared to previous object-oriented approaches. Our proposition is based on a family of hardware interfaces enabling to represent various interaction semantics and mapping configurations. Our approach is illustrated through the CORBA component model (CCM).

In this paper, we propose and study a new family of error-correcting codes. These achieve excellent error performance under an iterative decoding over the binary-input noisy channel and solves the memory space requirements problem of the non-binary LDPC decoders. We named this class of codes, Split non-binary LDPC codes. The main particularity of this new family of codes is that the variable and the check nodes are not defined over the same finite field GF(2p), like in the case of classical non-binary LDPC codes. The class of Split non-binary LDPC codes is obviously larger than that of existing types of codes, which gives more degrees of freedom to find good codes when the existing codes show their limits. We provide two examples of interesting split NB-LDPC codes.

In the scope of the US Department of Defense (DoD) Joint Tactical Radio System (JTRS) program, the portability and reconfigurability needs of software defined radios (SDR) required by the software communications architecture (SCA) can be resolved thanks to model driven architecture (MDA) and component/container paradigm to address a heterogeneous hardware and software architecture. In this paper, we propose SystemC transaction level modelling (TLM) to simulate platform independent model (PIM) and platform specific model (PSM) of SDRs, while keeping the component/container approach for applications portability. We show that SystemC 2.1 enables natively to simulate the waveform PIM specified in UML to obtain an executable specification, which can be reused to validate the SystemC TLM model of PSM. This latter allows radio platform virtualisation and true reuse of IPs models to validate earlier SDR waveforms and platforms

In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes presented in (D. Declencq and M. Fossorier, 2007). A particularity of the new algorithm is that it takes into accounts the memory problem of the non binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nm of values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to O(nmlog2nm), which starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation are quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual FER simulations.

We present in this paper an architectural model for implementing parallel and scalable low-density parity-check (LDPC) decoders. This model has been developed for targeting field-programmable gate array devices and system-on-chip (SoC) platforms. We present first the motivations of investigating a new hardware model for regular and irregular LDPC decoders. The code flexibility, the memory usage optimization, and an easy hardware integration have been taken into account. The construction of a specific class of codes (hardware-constrained LDPC codes) is then presented. Parallelization and pseudorandomness constraints of codes are particularly detailed. A complete description of our parallel and scalable hardware model suitable for reprogrammable architectures is then given. Simulation results are presented showing the efficiency of this model with both (3,6) regular and irregular codes