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Waldo C. Kabat

dblp:51/5756 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 60% Integrated circuit design · 40%
Theoretical computer science
1 paper
Logic in computer science · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis
combinational logic synthesis
0.011985
Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques · IEEE Trans. Computers 1985
Electronic design automation
logic synthesis
0.011985
Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques · IEEE Trans. Computers 1985
Integrated circuit design › digital circuit design
arithmetic circuit design
0.011981
On the Design of 4-Valued Digital Systems · IEEE Trans. Computers 1981
Integrated circuit design
digital circuit design
0.011981
On the Design of 4-Valued Digital Systems · IEEE Trans. Computers 1981
Integrated circuit design › digital circuit design
multivalued logic circuit
0.011981
On the Design of 4-Valued Digital Systems · IEEE Trans. Computers 1981
Electronic design automation › hardware verification and test
formal verification
0.011985
Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques · IEEE Trans. Computers 1985
Electronic design automation › hardware verification and test
hardware verification
0.011985
Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques · IEEE Trans. Computers 1985
Logic in computer science
many-valued logic
0.011981
On the Design of 4-Valued Digital Systems · IEEE Trans. Computers 1981

Methods — techniques the papers use, named apart from their topics

t-gate · 0.0i2l circuits · 0.0automated theorem proving · 0.0
YearPublicationVenuePosition
1992 Exploitation of Parallel Processing for Implementing High-Performance Deduction Systems
Anita Jindal, Ross A. Overbeek, Waldo C. Kabat
J. Autom. Reason.3
1986 Job-Shop Scheduling Using Automated Reasoning: A Case Study of the Car-Sequencing Problem
Bruce D. Parrello, Waldo C. Kabat
J. Autom. Reason.2
1985 Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques
abstract
Recent findings indicate that logic design still constitutes 50 percent of the total design effort, and yet few automated tools are being used in industry. The use of an automated theorem-proving system in the logic design process presents an intriguing addition to traditional design automation tools. This paper deals with the automated synthesis of combinational logic. The method consists of a theorem-proving implementation of a systematic, uniform procedure for the synthesis of an arbitrary switching function. Any multiple-valued (including binary) function can be synthesized in a top-down fashion using the functional blocks of the designer's choice. The method is general enough to allow for the choice of an arbitrary logic system and radix. Additional constraints of modularity, technology dependence, fault tolerance, and others may be imposed upon the design. It may also be possible to accommodate into this approach formal design verification, design for testability, functional level modeling, and formal analysis of race and hazard conditions.
Waldo C. Kabat, Anthony S. Wojcik
IEEE Trans. Computers1
1981 On the Design of 4-Valued Digital Systems
abstract
The availability of 4-valued I2L circuits presents a new perspective for digital systems designers. This correspondence explores several aspects of digital system design using 4-valued logic elements. An approach to designing the ith stage of an ALU employing these elements is presented. The realization of rudimentary ALU operations is shown using the T-gate as a universal building block System design based on both Post and Boolean 4-valued logics is discussed.
Waldo C. Kabat, Anthony S. Wojcik
IEEE Trans. Computers1