This paper presents a high-bandwidth memory (HBM) PHY interface employing a reconfigurable differentiator-based crosstalk cancellation (XTC) scheme to mitigate coupling noise arising in high-density silicon interposer channels. By introducing a novel analysis of RC-dominant channels from the perspective of group delay, the proposed XTC achieves precise delay matching by optimal differentiator parameter selection, without requiring additional hardware. Furthermore, the self-loading induced by multiple-aggressor XTC is compensated by reconfiguring the XTC scheme into a bandwidth extension scheme in which the bi-directional signaling nature of HBM interface is leveraged. Additionally, the merged adder with multiple-XTC and decision-feedback equalization (DFE) is proposed to provide improved offset and power performance. Fabricated in a 28-nm CMOS process, the prototype transceiver achieves an edge density of 15 Tb/s/mm and energy efficiency of 0.53 pJ/bit with high-density on-chip channels of 7.5-dB Nyquist loss. The proposed XTC technique reduces the crosstalk-induced jitter (CIJ) by four aggressors by 72.4% at a signal-to-crosstalk ratio of 0.45 dB, achieving an eye-opening of 0.42 UI at a$10^{-12}$bit error rate (BER).

This paper presents a single-ended four-level pulse-amplitude modulation (PAM-4) transceiver for next-generation high bandwidth memory (HBM) interfaces. Since HBM interfaces have over 1024 DQs, the interfaces need to improve energy efficiency and minimize area. The proposed PAM-4 transmitter employs capacitive drivers to extend bandwidth with low power and uses accumulation-mode NFET capacitors as AC coupling capacitors to reduce area. A high-level boosting technique (HLB) is introduced to compensate for the capacitance variation according to output voltage levels, thereby improving the ratio of level mismatch (RLM). A feed-forward equalization (FFE)-combined capacitive PAM-4 driver effectively removes inter-symbol interference (ISI), leading to higher data rates. To define the DC level without using dissipated static power, a ground-forcing technique is applied. The silicon interposer channel was emulated using a 5.9 mm on-chip wire. A prototype chip was fabricated in a 28 nm CMOS process and occupied 0.0039 mm2. The prototype achieves data rates of 16 Gb/s with an energy efficiency of 67.2 fJ/b/mm and RLM of 0.992.

This paper presents a single-ended, 4-level pulse amplitude modulation (PAM-4) receiver (RX) designed for maximum transition avoidance (MTA)-coded signaling. The RX employs a decision feedback power saving (DFPS) scheme and a 1-tap partial decision feedback equalizer (pDFE) for low-power memory interfaces. MTA-coded signaling eliminates maximum transitions. Utilizing this property, the proposed DFPS scheme reduces comparator power consumption by deactivating some comparators based on the previous pattern. Furthermore, the proposed pDFE, in a hardware- and power-efficient manner, selectively equalizes only the middle transitions, which creates the worst-case eye-opening due to switching jitter and inter-symbol interference (ISI) in MTA-coded signaling, resulting in an improved overall eye-opening. Simulation results show that the proposed scheme improves the timing margin from 0.43UI to 0.46UI for the LSB and from 0.47UI to 0.51UI for the MSB while achieving an 8.9% reduction in comparator power consumption.

A high input impedance read-out integrated circuit (IC) for DC measurements has been implemented. The proposed read-out IC consists of a capacitively coupled instrumentation amplifier (CCIA) and an incremental delta-sigma ($\Delta \Sigma )$analog-to-digital converter (ADC). An impedance boosting technique, combining the conventional positive-feedback loop with a proposed fine current compensation loop (FCCL), is introduced to enhance the input impedance of the CCIA. Additionally, the proposed structure chops the entire signal chain at a global chopping frequency of 13.2 kHz, which is higher than the 1/$f$corner frequency of the CCIA’s main amplifier. This approach further increases the input impedance of the CCIA and eliminates the need for RRL and an analog low pass filter (LPF), thereby reducing circuit complexity and area. Local auto-zeroing and correlated double sampling techniques are also used to suppress the offset and 1/$f$noise of the read-out IC. The 18-bit ADC operates at a sampling clock of 4 MHz with a third-order cascade of integrators (CoI) digital filter. Implemented in a 0.13$\mu $m CMOS process, the prototype chip occupies an area of 3.808 mm$^{2}$and draws 1.32 mA from a 5 V supply. The input impedance is boosted from 4.4 M$\Omega $to 5.1 G$\Omega $, corresponding to an impedance boosting factor of 1153. The measurement results show an input-referred noise of 2.4$\mu $V$_{\mathrm{RMS}}$with a conversion time of 0.076 ms. The input range of the ROIC is 4.8 V and it achieves the Schreier figure of merit of 164.9 dB.

This paper presents a single-ended hybrid digital-to-analog converter (DAC)-based transmitter (TX) using four-level pulse-amplitude modulation (PAM-4) for memory interfaces. The proposed hybrid DAC composed of voltage mode (VM) driver unit segments and current mode (CM) driver unit segments reduces the total number of unit segments without increasing complexity in impedance matching. Therefore, the hybrid DAC significantly reduces area and the associated power consumption. Digital signal processing (DSP)-based feed-forward equalization (FFE) provides precise and flexible equalization. The proposed linearity enhancement technique compensates for additional non-linearity caused by short-length devices in the CM driver segments. The proposed TX operating at 40Gb/s/pin consumes 30.9mW with 1.0/0.9/0.15V supply voltages, achieving 0.77pJ/bit energy efficiency and a level separation mismatch ratio (RLM) of 0.989. The TX occupies an active area of 0.023mm2.

In multi-lane interfaces using single-ended signaling such as memory interfaces, far-end crosstalk (FEXT) noise of the aggressor signal severely degrades signal integrity of the victim signal. A circuit for crosstalk cancellation (XTC) can reduce FEXT noise. However, the channel spacing makes the flight time difference between the forward and FEXT signals. As a result, the residual FEXT can remain. To further minimize the residual FEXT, this study proposes an XTC method to adjust the amplitude and timing independently. The timing is adjusted according to the passive element’s value of the differentiator, and the amplitude is varied by using the high-frequency boosting circuit. Moreover, a continuous-time linear equalizer (CTLE) and a 1-tap decision feedback equalizer (DFE) are applied to reduce inter-symbol interference. A prototype chip of 2-lane receiver was fabricated in a 55-nm CMOS process to verify this scheme. Using the proposed XTC, CTLE, and 1-tap DFE, timing margins of 0.21 UI and 0.36 UI were achieved in 6-mil and 15-mil channel spacings at 6.4 Gb/s, both at a bit error rate of$10^{-12}$.

This presents a fully-synthesizable cyclic Vernier time-to-digital converter (TDC) which cancels the offsets by a quad-edge offset cancellation (QOC) scheme. The system delays its internal clocks and uses the clock offsets to compensate for many types of offsets altogether, which includes the wiring mismatches, the duty cycle skews, and the long-term jitters of the clocks. During calibration, the QOC-TDC measures the offsets of the clock paths. The measured offsets are then canceled in the normal mode. An additional scheme of coarse-fine boundary synchronization further enhances the output monotonicity. Consisting of only standard library cells offering fully-automated implementation, the QOC-TDC achieves a 19-bit range, a 4.5-ps resolution, and the throughput of 22MS/s, while drawing 3.4mW from a 1. 0V supply, as shown by the post-layout simulations in 28nm CMOS.

The dual-rank configuration is one of the parallelization methods to increase the memory capacity for mobile applications. However, the stub mainly composed of the redistribution layer causes resonance reflections and its reflection interval reaches the bit period, which distorts signal and limits the signal bandwidth. A single-ended duobinary transmitter that utilizes the reflection is presented for dual-rank mobile memory interfaces where reflections dominate. The reflection is included in the transfer function for duobinary modulation, which allows the transmitter to have a wide eye opening and high energy efficiency. Two-tap reverse feed-forward equalization and slew-rate control are used to support the duobinary modulation in combination with the reflection. A prototype chip fabricated in a 65 nm CMOS process has an area of 0.0378 mm2and consumes 1.24 pJ/bit. It is verified at data rates of 8, 9 and 10 Gb/s/pin where the flight time of the 9 mm stub is 55.6 ps.

This work presents a low-power and fast-locking digital 1.6GHz quadrature clock generator (QCG), which mainly consists of a novel ping-pong phase detection (PPD) controller with a pair of latch-based phase detectors. The proposed PPD scheme compares generated clock signals from a digitally controlled delay line (DCDL) with an input clock for fast coarse lock, resulting in a short locking time. Post-layout simulations of an implementation in 28nm CMOS technology suggest that the proposed work can lock within 13 cycles and produce 4-phase 1.6GHz quality output clocks, which supports a data rate of 6.4Gbps. It achieves an RMS jitter of 1.65ps and an effective peak-to-peak jitter of 1.12ps, offers power efficiency of 0.25mW/Gbps, and occupies an area of 0.00247mm2.

In this paper, a quadrature signal corrector (QSC) with high accuracy and fast correction for memory interfaces is presented. An adaptive delay gain controller in the QSC adjusts each delay gain of four digitally controlled delay lines (DCDLs) separately depending on skew between the quadrature clocks, resulting in short correction time together with low residual skew. To validate the effectiveness of our QSC in memory interfaces, a quarter-rate single-ended 1-tap decision feedback equalizer (DFE) with the QSC was fabricated in a 65nm CMOS process. Using the adaptive delay gain controller, the QSC reduced the skew between the 3 GHz quadrature clocks from a maximum of 21.2 ps to 0.8 ps while correction time was reduced by a factor of 3.9 compared to that without using the adaptive delay gain controller. At 12 Gb/s, the DFE using our QSC achieved a BER of 10-12with an eye width of 140 mUI when the input clock skew is 13.2 ps.

A high-precision DC measurement read-out integrated circuit (ROIC) is implemented from a low-noise capacitively-coupled chopper instrumentation amplifier (CCIA) followed by a high-resolution incremental discrete- time delta-sigma modulator (DTΔΣM) analog-to-digital converter (ADC). In this paper, a doubled sampling-time (DST) incremental DTΔΣM is proposed to reduce CCIA's bandwidth. Through the proposed technique, the power consumption of the traditionally power-hungry IA is halved, while the desired system specifications such as output data rate (ODR) and effective resolution (ER) are maintained. Implemented in a standard 0.13-μm CMOS process, the ROIC's effective resolution is 21.0 bit at gain 1 and that of 19.8 bit at gain 64. The analog part draws only 114.4 μA from 3-V supply.

In this paper, a 20Gb/s dual-mode four-level pulse amplitude modulation (PAM4)/non-return-to-zero (NRZ) single-ended voltage-mode transmitter is proposed. Its output drivers are composed of 60 basic source-series terminated (SST) driver units and 12 additional pull-up (PU) driver units. The additional PU driver units are used to reduce the eye height difference between four amplitude levels of PAM4. Implemented in 65nm CMOS technology, the active area of the transmitter is 0.06mm2including the clock buffer and IQ generator. It draws 61.5mW at 20Gb/s during PAM4 operation and 72mW at 10Gb/s during NRZ operation.

This paper describes a 16-bit incremental analog-to-digital converter (ADC) for sensor applications. To implement a wide applicable ADC, which can be used in the commercial case, a full-on-chip voltage reference for the delta-sigma (ΔΣ) ADC is incorporated. The swapping digital-to-analog converter (DAC) is proposed in the loop-filter to minimize the noise effect of the voltage reference, which can directly deteriorate the effective resolution (ER) of the readout system. Furthermore, gain programmable characteristic is embedded in the ADC for various applications. Measurements show that the ADC achieves 16.07-bit ER and 10 LSB integral nonlinearity (INL), while dissipating only 18 μA current from a 3.3 V supply. The ADC was fabricated in a 0.18-μm standard CMOS process with a 0.182 mm2active area.

The increasing data rate of serial links makes it difficult to match timing constraints of serializers in transmitters. Delay compensation clock buffers can alleviate this issue by matching the timing between data and clock. However, these buffers consume significant power and become sources of noise to the transmitter output. The problem is more serious for serializers other than 2n:1, and using only 2n:1 serializer could be a limitation on system design. In this paper, a 20:1 serializer using two calibration feedback loops is presented to solve this issue and reduce power consumption. The two loops detect the phase difference between data and clock, and automatically align the clock phase to the center of the data phase. The loops eliminate the power-consuming clock buffers on the critical clock path and operate at maximum quarter rate, enabling the transmitter to have low power consumption and high performance. A 6.4 Gb/s serializer prototype is fabricated in 55-nm CMOS process with a 1.2 V supply voltage. It achieves 97.5 ps eye width, which is 62.4% of a unit interval (UI) using PRBS-7 data, and its energy efficiency is 1.60 pJ/bit.

This paper presents a sound activity detector embedded low-power MEMS microphone readout interface for speech recognition. The proposed readout interface exploits the sound activity detector to automatically switch to active/standby mode depending on whether a sound activity is present or not. Since voice recognition applications are mostly in standby mode, standby power consumption is of greater importance than active power consumption. Our readout interface consumes only 14 μA in standby mode, which can significantly extend battery usage time. Also, a fast wake-up feature is provided. In active mode, the readout interface converts the microphone input signal to a high-resolution digital signal. The proposed circuit is fabricated in a 0.18 μm CMOS process. The measurement is performed using a differential piezo MEMS transducer. It achieves A-weighted signal-to-noise ratio of 62.6 dBA and a dynamic range of 104.5 dB.

A quadrature clock corrector uses relaxation oscillators to detect duty-cycle and quadrature phase errors by transforming them into pairs of frequencies, which are then digitized and compared. It achieves good detection accuracy and can detect a wide range of duty-cycle and quadrature phase errors. The prototype is implemented in a 55-nm CMOS process with a supply voltage of 1.2 V and occupies an area of 0.003 mm2. The experimental results show that the operation range is from 1 to 3 GHz, the power efficiency is 0.79 mW/GHz, the maximum duty-cycle error is 0.8% at 3 GHz, and the maximum quadrature phase error is 1.1° at 3 GHz.

In this paper, we propose a dynamic comparator that improved the operation performance of receiver (RX) with the effort to reduce power consumption. It is implemented via double-tail StrongARM latch comparator with an active inductor and efforts are made to minimize power consumption for high-speed resulting in better energy efficiency at the targeted high frequency. In this regard, our comparator is suitable for memory application RX to satisfy both low-power and high-speed. It is applied to the single-ended RX designed with a continuous-time linear equalizer, a clock generator and a quarter-rate 2-tap decision-feedback equalizer which is appropriate for the high-frequency memory application. Compared to the conventional one, our design, fabricated in 55nm CMOS process, provides an improvement of 7% in unit interval (UI) margin under the same power consumption and receives up to 10Gb/s PRBS15 data at BER < 10-12 with 0.4 UI margin and energy efficiency of 0.67pJ/bit.

The size and power dissipation of an infrared imaging system can be reduced by the use of uncooled microbolometers; but the nonuniformity of the microbolometer makes such imaging systems heavily reliant on complicated calibration techniques, incurring an overhead which is particularly significant in low-cost, compact devices. We therefore propose a shutter-based successive-approximation calibration loop, which avoids the need to implement correction tables in software on an external processor. Prototype imager, consisting of an 80 × 82 pixel infrared focal-plane array and readout circuitry, has been implemented, and the experimental results confirm that our on-chip autocalibration approach compensates effectively for fixed pattern noise caused by the nonuniformity of the microbolometers.

A load variation tolerant readout interface with embedded gain control and discrete power control to improve the linearity for a MEMS capacitive microphone is presented. The current consumption of the readout circuit is controlled discretely by digital codes as the loading capacitance changes while maintaining the operating point of each MOSFET in the readout circuit. The proposed discrete power control scheme improves 4.3 dB of total harmonic distortion when the loading capacitance decreases by 75 % in comparison with the conventional bias control method. The readout circuit was fabricated in 0.18 μm CMOS process. Post-layout simulation results show that total harmonic distortion is -101.2 ~ -102.4 dB and power dissipation is 4.7 ~ 15 mW from 3.3 V supply when the loading capacitance changes from 5 pF to 20 pF.

The proposed 1.8-V 10-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for electrocardiographic (ECG) monitoring applications has two operation modes suitable for the dichotomous activity of ECG signals: full and reduced switching modes. MSBs tracking and LSBs extrapolation run in full and reduced switching mode, respectively, for smooth mode changes adaptive to the input activity. A prototype chip was fabricated in 0.18-μm CMOS technology. The suitability of the proposed adaptive switching was proved by the measurements that the total power consumption was reduced by 15.3% compared to the full switching case.

In this paper, we propose a low power transceiver (TRx) suitable for a wired intra-body area network (BAN) communication. The proposed transceiver is designed with relaxation oscillator which is appropriate for this low frequency (<; 50MHz) application. To lessen the complexity of building this BAN system, we use clock edge modulation (CEM) data as sending or receiving data, and this allows the transceiver to operate without reference clock. The relaxation oscillator in this transceiver is designed to be able to generate CEM data pattern as well as a clock, so this can minimize power consumption in designing additional block related to transmission. Proposed circuit operates up to 36MHz with 1.0V supply voltage. It consumes 1.26uW at an input data rate of 10Mbps and achieves 0.13pJ/bit of energy per bit even though the circuit is implemented in a 0.18μm CMOS technology.

This paper proposes a phase shift keying (PSK) demodulator with a decision feedback phase-locked loop. It shrinks the size of capacitor without its performance degrade, compared to that of the conventional PSK phase-locked loop. When a certain threshold is reached by a decision summation, the negative feedback on the loop filter's control voltage is provided. Modeled and simulated in VerilogA, the working speed of the proposed circuit is up to 27.12 Mbps, and it can operate for an infinite period of time with the reduced size of the capacitor.

A power-efficient programmable-gain control function embedded Delta-Sigma (ΔΣ) analog-to-digital converter (ADC) for various smart sensor applications is presented. It consists of a programmable-gain switched-capacitor ΔΣ modulator followed by a digital decimation filter for down-sampling. The programmable function is realized with programmable coefficients of a loop filter using a capacitor array. The coefficient control is accomplished with keeping the location of poles of a noise transfer function, so the stability of a designed closed-loop transfer function can be assured. The proposed gain control method helps ADC to optimize its performance with varying input signal magnitude. The gain controllability requires negligible additional energy consuming or area occupying block. The power efficient programmable-gain ADC (PGADC) is well-suited for sensor devices. The gain amplification can be optimized from 0 to 18 dB with a 6 dB step. Measurements show that the PGADC achieves 15.2-bit resolution and 12.4-bit noise free resolution with 99.9 % reliability. The chip operates with a 3.3 V analog supply and a 1.8 V digital supply, while consuming only 97 μA analog current and 37 μA digital current. The analog core area is 0.064 mm2 in a standard 0.18-μm CMOS process.

A phase-dependent gain-transition correlated double-sampling technique is proposed and applied to a 10-bit 75-MS/s pipelined analog-to-digital converter. This reduces the accumulation of predictive error of each multiplying digital-to-analog converter stage due to the finite gain of the operational amplifiers, without the need for additional capacitors and switches at the input. With a 10-MHz sinusoidal input, a prototype fabricated in a 0.13- μm CMOS process has a 56.90 dB signal-to-noise plus distortion ratio (SNDR) and a 64.57 dB spurious-free dynamic range (SFDR) at 75 MS/s. For a 37 MHz input at full sampling rate, the SNDR and SFDR are 55.01 and 60.77 dB, respectively. The IC has an active area of 0.65 mm2and consumes 32 mW with a 1.2 V supply.

In wide fan-in dynamic domino gates, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes which introduces a significant power penalty. In this paper, we propose a pulse domino technique to reduce the overall power consumption of a wide fan-in dynamic gate by having static-like switching behavior at the dynamic node, the gate input and the output terminals. Dynamic multiplexers designed and simulated in 90-nm CMOS are used to demonstrate the energy effectiveness of the proposed design style.

To suppress the ground bounce noise with a minimal wake-up time penalty, a three-step turn-on strategy and its corresponding power-gating structure are proposed. During the circuit's meta-stable region of operation, specifically, the amount of current flowing through the sleep transistors is precisely controlled while the virtual or circuit power supply is quickly boosted when the internal nodes of the circuit are stable. In 65 nm CMOS technology, simulation results demonstrate that our technique reduces the peak amplitude of the ground bouncing noise by up to 94% as compared to the conventional abrupt turn-on technique.

Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV/sup 2/ rate for CMOS switching power. Early engineering research in this field, which became generally known as adiabatic computing, focused on the asymptotic energetics of computation, exploring VLSI designs that use reversible logic and adiabatic switching to preserve information and achieve nearly zero power dissipation as operating frequencies approach zero. Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. Although their origins can be traced back to the early adiabatic circuits, these charge-recovering systems approach energy recycling from a more practical angle, shedding reversibility to achieve operating frequencies in the hundreds of MHz with relatively low overhead. Among other charge-recovery designs, researchers have demonstrated microcontrollers, standard-cell ASICs, SRAMs, LCD panel drivers, I/O drivers, and multiGHz clock networks. In this paper, we present an overview of the field and focus on two chip designs that highlight some of the promising charge recovering techniques in practice.

A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 um CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.

We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which sleep transistors are turned on in a non-uniform stepwise manner. Our power gating structures reduce the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground. Experimental simulation results with PowerSpice fixtured in a package model demonstrate the effectiveness of the proposed power gate switching noise reduction techniques.

In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have been designed in SCAL-D, a true single-phase adiabatic logic family. Fabricated in a 0.5-/spl mu/m standard n-well CMOS process, the chip has an active area of 0.47 mm/sup 2/. Correct chip operation has been verified for clock rates up to 140 MHz. Moreover, chip dissipation measurements correlate well with HSPICE simulation results. For a selection of biasing conditions that yield correct operation at 140 MHz, total measured average dissipation for the multiplier and the power-clock generator is 250 pJ per operation.

This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-phase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal power-clock waveform that is generated on-chip. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and self-test circuitry approaches 130pJ per operation at 200MHz. Our 11,854-transistor chip has been fabricated in a 0.5&mgrm standard CMOS process with an active area of 0.470mm$^2$. Correct chip operation has been validated for operating frequencies up to 130MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations.

Recently discovered high-speed single-phase adiabatic logic families require efficient sinusoidal power-clock generators. In this paper we propose a low-power resonant clock-generator built around a zero-voltage switching push-pull power conversion topology. We describe a novel energy-efficient control circuit for this power converter, based on an asynchronous CMOS state machine. We also describe an integrated sub-micron CMOS implementation of our power converter and control circuits. Simulation results show efficiencies in excess of 90%, even under suboptimal tuning conditions, for frequencies over 200MHz. We have fabricated our clock generator in a 0.5�m standard CMOS process. Using an external surface-mount inductor as the resonant element, we have verified the correct operation of the clock generator when driving a singlephase adiabatic 8-bit multiplier.

Dynamic logic families that rely on energy recovery to achieve low energy dissipation control the flow of data through gate cascades using multiphase clocks. Consequently, they typically use multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to their high complexity and clock skew management problems. In this paper, we present TSEL, the first energy-recovering (a.k.a. adiabatic) logic family that operates with a single-phase sinusoidal clocking scheme. We also present SCAL, a source-coupled variant of TSEL with improved supply voltage scalability and energy efficiency. Optimal performance under any operating conditions is achieved in SCAL using a tunable current source in each gate. TSEL and SCAL outperform previous adiabatic logic families in terms of energy efficiency and operating speed. In layout-based simulations with 0.5 /spl mu/m standard CMOS process parameters, 8-bit carry-lookahead adders (CLAs) in TSEL and SCAL function correctly for operating frequencies exceeding 200 MHz. In comparison with corresponding CLAs in alternative logic styles that operate at minimum supply voltages, CLAs designed in our single-phase adiabatic logic families are more energy efficient across a broad range of operating frequencies. Specifically, for clock rates ranging from 10 to 200 MHz, our andbit SCAL CLAs are 1.5 to 2.5 times more energy efficient than corresponding adders developed in PAL and 2N2P and 2.0 to 5.0 times less dissipative than their purely combinational or pipelined CMOS counterparts.

Adiabatic circuits offer a promising alternative to conventional circuitry for low energy design.Their operation is nevertheless subject to fundamental energy-speed trade-offs, just like any other physical realization of boolean logic.Thus, adiabatic circuits with very low energy consumption at low frequencies fail to function at high operating frequencies.Conversely, high-speed adiabatic circuits tend to be dissipative at low clock rates.This paper describes SCAL, a single-phase source-coupled adiabatic logic family that operates efficiently across a wide range of operating frequencies.In layout-based simulations with O&m CMOS process parameters, pipelined carry-lookahead adders developed in our logic function correctly from 1OMHz up to 280MHz.Our SCAL adders are less dissipative than corresponding designs in alternative adiabatic families that remain functional across the same frequency range.Moreover, they are about as dissipative as other adiabatic circuits that are geared towards very efficient operation at low frequencies.In comparison with their CMOS counterparts, our SCAL adders are 3 to 10 times more energy efficient.

In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multi-phase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to clock skew management problems.