This paper presents a fully integrated NMOS stimulator using a hybrid dynamic bulk biasing technique (HDBT) and a charge-pump-like control technique (CCT) in a 180-nm bulk CMOS technology. HDBT integrates terminal-voltage-dependent and logic dynamic bulk biasing to set the bulk bias voltage according to the electrode voltage. CCT adds a DC voltage to the gate terminal through a diode and capacitor to help turn on the NMOS transistor. It helps turn off the transistor by shorting the source and gate terminals together and applying two diodes across the drain and source terminals. To achieve an electrode voltage higher than the breakdown voltage of substrate diode ($V_{\mathrm {BD}}$) with an independent power supply, a high voltage tolerant switch is proposed with HDBT and CCT. A high voltage interface is also proposed, utilizing the capacitor adaptive biasing, to overcome the limitation of$V_{\mathrm {BD}}$between the high and low voltage domains and to accommodate the variation of electrode voltage. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves a maximum electrode voltage ($V_{\mathrm {E,MAX}}$) of 18.74V under a 3.3-V supply, with a highest$V_{\mathrm {E,MAX}}$/$V_{\mathrm {BD}}$ratio of 1.27 than state-of-the-art stimulators, including non-standard technology designs. In a continuous output test mode over 10million cycles, the variation of$V_{\mathrm {E,MAX}}$is less than 150mV. The measured maximum residual voltage on the capacitor is 13.55mV.

Abstract The forthcoming 6G technology offers significant potential for the advancement of the smart grid domain. 6G promises ultra-low latency, higher data transfer rates, native Artificial Intelligence (AI) support, enhanced connectivity, and improved security for smart grids. Smart grids are vulnerable to cyberattacks, such as Distributed Denial-of-Service (DDoS) attacks, posing a significant threat to grid functionality. To address security concerns, smart grids implement intrusion detection systems (IDS), but detecting novel attacks such as subtle multi-domain DDoS attacks through traditional IDS is challenging. To enhance grid security, Deep Learning (DL) techniques can be utilized to identify deviations from normal network traffic and detect cyberattacks. However, training DL models with sensitive user data may violate data privacy regulations, necessitating novel approaches. Federated Learning (FL) offers a privacy-focused solution enabling smart meters to train DL models with locally generated data and make predictions at the edge. In this work, we implement a novel approach, integrating AWS cloud and FL for privacy-preserving DDoS attack detection in 6G-ready smart grids. Our approach aims to leverage the scalability of AWS cloud and advanced communication capabilities of 6G for efficient, secure, and cost-effective cyberattack detection. By implementing our approach in a local environment and the AWS cloud, we investigate the stability and robustness of the approach for large-scale cloud deployments. In addition, using statistical tests, we confirm that the performance between local and cloud implementations is consistent, and that the proposed approach is suitable for deployment in the upcoming 6G-enabled smart grids, where consistent performance is critical.

A robust, cascaded unit cell-based programmable gain amplifier (PGA) with precise and accurate dB-linear characteristics using the exponential approximation of the MOS transistor is presented. The exponential function is precisely generated for the desired gain range by exploiting the sub-threshold characteristics of load transistors in the proposed unit-cell. The proposed PGA has dual-mode gain tunability using analog voltage control and 5-bit digital control. The proposed PGA achieves a gain range from −37 dB to +39 dB with wide bandwidth and very low power consumption. The proposed dB-linear PGA is designed and fabricated in a standard 40nm CMOS technology. The measurements demonstrate that the proposed PGA can achieve a wide dB-linear gain range of 76 dB for 32 digital gain settings and a gain error of less than ±0.5 dB. At the maximum gain setting, the PGA exhibits a bandwidth of 1.1 MHz, input referred noise of 29.8 nV/$\surd $Hz, output P1dB of −4.7 dBm, and consumes only$167~\mu $W of power from a 1.1 V supply. The core area occupied by the PGA is only 0.003 mm2.

Active learning, which aims to enhance modeling efficiency, precision, and cost effectiveness through selective labeling, is emerging as a promising strategy for analog circuit modeling. However, analog circuits are constrained by strict functional and technological limitations, resulting in scarcity of data for modeling, and additional data acquisition involves expensive and time-consuming simulations. For efficient and effective active learning for analog circuit modeling, our research analyzes data-driven initial sampling techniques which lays the foundation for the active learning process. Our experiments reveal that these initialization strategies expedite the learning process, decrease the demand for extensive simulations, and produces more accurate models. Furthermore, the results demonstrate that active learning techniques, which uniformly sample the design space, tend to benefit from distance-based initialization technique.

A reconfigurable fully integrated automatic gain control (AGC) amplifier is presented which is based on a dual mode continuous gain adjustment variable-gain amplifier (VGA). The VGA is realized based on the current-steering structure, achieving a linear-in-dB gain tuned by AGC’s feedback voltage. A current division active load is proposed, which provides additional gain control range and realizes gain robustness to process and supply variations without extra calibration. Simulated with Cadence IC, the maximum gain variations due to process and supply variations are 3.5 dB and 2.6 dB, respectively. By using dual mode gain tuning technique, the VGA achieves a total gain range of 68.2 dB. Both bandwidth and gain of the VGA are adjusted independently. The AGC is realized in UMC 55-nm CMOS technology with 0.026 mm2core area. With the current division ratio K of 0.5, the proposed VGA achieves a linear-in-dB gain of 42.2 dB (−30.0 to 12.2 dB) with less than 0.79 dB error. The −3 dB bandwidth can be adjusted from 80 MHz to 140 MHz and is insensitive to gain variations. The power dissipation is from 2.9 mW to 4.5 mW. This design features bandwidth scalability and the gain independent of bandwidth to achieve various applications.

Clients of permissionless blockchain systems, like Bitcoin, rely on an underlying peer-to-peer network to send and receive transactions. It is critical that a client is connected to at least one honest peer, as otherwise the client can be convinced to accept a maliciously forked view of the blockchain. In such aneclipse attack, the client is unable to reliably distinguish the canonical view of the blockchain from the view provided by the attacker. The consequences of this can be catastrophic if the client makes business decisions based on a distorted view of the blockchain transactions. In this paper, we investigate the design space and propose two approaches for Bitcoin clients to detect whether an eclipse attack against them is ongoing. Each approach chooses a different trade-off between average attack detection time and network load. The first scheme is based on the detection of suspicious block timestamps. The second scheme allows blockchain clients to utilize their natural connections to the Internet (i.e., standard Web activity) to gossip about their blockchain views with contacted servers and their other clients. Our proposals improve upon previously proposed eclipse attack countermeasures without introducing any dedicated infrastructure or changes to the Bitcoin protocol and network, and we discuss an implementation. We demonstrate the effectiveness of the gossip-based schemes through rigorous analysis using original Internet traffic traces and real-world deployment. The results indicate that our protocol incurs a negligible overhead and detects eclipse attacks rapidly with high probability, and is well-suited for practical deployment.

This paper presents a new inductorless 6-GHz variable gain differential transimpedance amplifier (VGDTIA) with voltage bias controlled variable gain designed using TowerJazz 0.18-μm SiGe BiCMOS technology (using CMOS only). It consists of a modified cross-coupled regulated cascode preamplifier stage (CCRGC) and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback (CVG3F). The design has a transimpedance gain range of 20.6-60.5 dBΩ with constant bandwidth of 6.6 GHz and a dynamic range of 41.2 μA to 1.1 mA. The power consumption is 33.9 mW from 1.8 V supply, and the input referred noise current is 10.4 pA/√Hz. This design is compact and the core area is 100 μm × 85 μm.

In this brief, an analytical model for the reliability-oriented design of injection-locked frequency divider (ILFD) is proposed. It is able to provide a clear evaluation of startup condition in the ring oscillator (RO)-based ILFD, which has not been clearly defined with the conventional zero-pole theory. A new startup condition analysis is presented and applied in designing an ILFD to achieve a reasonable compromise between a robust startup condition and a wide locking range. To verify this theory, a prototype is fabricated using a standard 0.18 μm CMOS process, maintaining a reliable startup over potential variations of manufacturing or working conditions. The experimental results at industrial temperature ranges under different supply voltages suggest that the proposed divider is able to work robustly from 0.19 to 1.24 GHz with a maximum power consumption of 0.246 mW from a 1.2-V supply, while occupying a silicon area less than 20 x 30 μm2.

The adoption of IoT enabled devices have led to higher risks of EMI issues, especially in their power management. Particularly, rectifiers for IoT devices are especially concerning. To mitigate this, one approach is to use wide-bandgap semiconductor devices for power management, which reduces the devices' susceptibility and emission of conducted EMI. One such example are GaN semiconductors. However, for low voltage, low frequency systems, the literature concerning GaN performance with regards to conducted EMI have been sparse. This is particularly important for industries such as the medical field which might require low voltage power circuits with components more adept to handling EMI. In this paper, an evaluation will be carried out to compare transistors' performance in the design of a low voltage, low frequency rectifier of 12 Vac at 50 Hz. The results of the simulation using IGBT, GaN FETs and MOSFETs are then shown and discussed.

One of the problems faced in the product de-velopment design cycle is the requirement that the devices would have to be electromagnetically compliant. With more and more pyroelectric sensors implemented in smart systems due to their attractiveness in reducing costs and increasing energy conservation, there have been more instances of these sensors failing due to EMI. As such, there is an increasing need to explore the EMS of these sensors, especially when they are implemented in IoT enabled devices. This paper therefore seeks to explore the EMS of pyroelectric sensors to conducted noise injection in IoT applications. This is done by devising a noise injection circuit to be implemented in the setup. The experiment and the results of this setup is presented accordingly.

VLC systems often requires costly devices and a lengthy design process due to its high performance and precision requirement. In this work, low-cost devices and rapid prototyping have been adopted to realise a system which can transmit real time video streaming. A VLC transmitter and receiver circuit has been designed and implemented. The full system consists of a mechanical enclosure, which was fabricated using rapid prototyping techniques such as 3D printing and laser cutting, electrical circuitry system and the optical modules. The prototype was thus able to transmit video signals compatible with the National Television System Committee (NTSC) standard, up to a distance of 3.1 m.

RF technologies has facilitated communication including audio, images, video and data transmission. However, the RF spectrum is getting increasingly crowded, and alternative methods to transfer data need to be explored. In this paper, software-hardware co-design is implemented to design the audio data synchronization and transmission for an optical-through-air transceiver system. Besides audio transmission, the performance of the VLC system is verified through testing serial data transmission and text transmission. The experimental results show that the VLC system can achieve up to 4 Mb/s data rate using OOK modulation with red light. This system provides a practical step-by-step guidance for setting up a VLC system for data transmission.

This paper presents the design of a compact 60-GHz phase shifter that provides a 5-bit digital phase control and 360° phase range for beam-forming systems. The phase shifter is designed using the proposed cross-coupled bridged T-type topology and switched-varactor reflective-type topology. The topologies are analyzed using a small-signal equivalent circuit model. Furthermore, the design equations are derived and investigated. To validate the theoretical analysis, 60-GHz 5-bit 360° phase shifters are designed in a commercial 65-nm CMOS technology. The fabricated 360° phase shifter features good performance of 32 phase states from 57 to 64 GHz with an rms phase error of 4.4°, a total insertion loss of 14.3 ± 2 dB, an rms gain error of 0.5 dB, P1dB of better than 9.5 dBm, and the power consumption of almost zero. To the best of our knowledge, the designed 360° phase shifter with the size of 0.094 mm2is the smallest 5-bit passive phase shifter at frequencies around 60 GHz.

Diminishing bitline sensing margin at low voltage condition is one of the most challenging design obstacles for reliable SRAM implementation in nano-scale CMOS technologies. This paper presents a self-biased design technique that improves the bitline sensing margin during the read operation by sourcing a current which is the same as the total leakage along each bitline. It is able to automatically track changes in supply voltage, operating temperature and die-to-die process variations. Furthermore, a 9T SRAM cell is utilized to ensure that bitline leakage is data-independent. Simulation and measurement results using 65 nm CMOS process show that the proposed technique enlarge the bitline swing over a wide range operating temperature and operates successfully down to the supply voltage of 0.18 V.

Real time spike detection is the first critical step to develop spike-sorting for integrated brain circuits interface applications. Nonlinear Energy Operator (NEO) and absolute thresholding have been widely used as the spike detection algorithms where NEO has a better performance measured by the probability of detection and false alarm. This paper proposes a hybrid spike detection algorithm incorporating both spike detection algorithms to reduce the power and to keep the detection rate the same as that of NEO. In the proposed algorithm, the absolute thresholding is performed first to detect a potential spike. Once a potential spike is detected, NEO is executed to check whether the detected spike by absolute thresholding is valid. Since NEO is conditionally conducted, this reduces the overall power consumption. The simulation shows that the proposed hybrid method improves the power consumption by 54.48% compared to NEO in 65 nm CMOS technology.

Real time spike detection is the first critical step to develop spike-sorting for brain-IC interface applications. For implantable VLSI implementation, spike detection hardware must consume low power and at the same time ensure high true positive probability while having as few false alarms as possible. Currently, Nonlinear Energy Operator (NEO) and absolute thresholding are the two most widely used spike detection algorithms where NEO has a slightly better performance measured by areas under the receiver operating characteristic (ROC) curves. This paper revisits these two algorithms and quantitatively points out that NEO is in fact much better than absolute thresholding. We also propose a hybrid algorithm that offers similar accuracy as NEO but only requires 11% of power consumption.

We proposed a NEMS-based anchorless memory structure with two stable mechanical states (Up and Down) for retaining data even at high operating temperate (>200°C) [5]. Compared to the conventional anchored devices, the anchorless structure offers better scalability and can operate at lower supply voltage, which is more desirable for integration with CMOS processes. This work addresses several issues in the previous NEM memory array implementation such as shuttle oscillation due to electrostatic pendulum and non-polarity write operation. We propose a 128 × 128 NEM memory array consisting of NEM memory cells and CMOS read/write control circuits. Our proposed read/write scheme with the two-level gate control eliminates the non-polarity write issue and achieves 32% power and 14% delay improvements when compared to the previous control scheme.

Current-mode CMOS stimulation systems have offered unprecedented opportunities for accurate and high through put in-vitro and in-vivo physiological studies. As these circuits are in long term contact with living organisms, they must be flexible, safe and power efficient. Any mismatch in biphasic current pulses will result in charge imbalance, leading to tissue/cell damage. Therefore, it is the most important to maintain the balance of the charge injected and retracted by the anode and the cathode, respectively. This work first adjusts the body biasing voltage of the anode to match with the cathode current. It is robust, process-variation-aware and can reduce the imbalanced current to less than 1%. Second, any residue charge at the stimulation site is retracted only when it reaches a critical value. This process is performed in the background and thus does not disturb the front-end operation. Overall, it can achieve less than 0.4 nA DC error current and thus is a suitable candidate for long term stimulation applications.

In this work, we propose two decision techniques that interchange between MIMO and diversity schemes for improving shadowing and alignment problems. In a visible-light communication (VLC) system, the transmission nature can be of two types: (1) all LEDs transmit the same signal stream simultaneously; or (2) each LED transmits different parts of a signal stream independently. The MIMO-diversity technique detects and computes the transmitted signal power during reception and conditionally informs the transmitter to switch between Type (1) and Type (2) transmission. Two experimental models have been tested to show the feasibility of such a technique. In the first model, we constructed a full transceiver and uses a switch IC to switch between MIMO and diversity. The second model uses a microcontroller and software decision to switch between two COM ports, each of them dedicated to MIMO and diversity output respectively. Results suggest that shadowing and alignment problems commonly encountered in visible-light communication systems can be readily solved using these methods. A focusing equation has also been formulated to predict signal intensity more accurately. The focusing gap between the concentrator and the photodiode is taken into consideration during channel computation.

We propose a free-space optical system to replace wireless LAN in commercial and residential premises. Closing the last mile using wireless optical (WOP) communication provides the advantages of a cableless environment, mobility freedom, and faster data transfer rate. Trunk optical signals from the metropolitan core terminate at the optical control panel (OCP) in premises, after which signals are filtered, recoded, and emitted via LEDs to the different areas of the house or office. Photoreceivers, on the other hand, absorb light signals and convert them back to electrical signals for the devices. Since light has become the medium of communication, a few devices have been proposed so that transmission and reception of optical signals are optimized.

This paper presents a novel cross-coupled current conveyor based CMOS transimpedance amplifier (TIA) design to obtain an input capacitive load insensitive and very low noise structure. The proposed structure is presented with an implementation in GlobalFoundries' 0.18- μm 1.8-V industry compatible CMOS technology. The whole TIA circuit consumes only 31.5 mW of dc power. Measured results show a -3 dB bandwidth of about 4 GHz with a 0.25 pF photodiode capacitance. The single-ended transimpedance gain for positive output port is 46 dB Ω. The measured single-ended input-referred noise current spectral density is kept below 18 pA/√{Hz} within the TIA frequency band. The optical sensitivity for a bit-error-rate of 10-12is -15 dBm with 4.25 Gb/s 231-1 proactive Reed-Solomon bypass data pattern. This cross-coupled structure also facilitates building an input-insensitive differential TIA. The simulation result shows a stable frequency response over a wide range of input capacitance from 0.05 to 0.5 pF.

Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry. Thus, robust, high-speed and low-powerMLsense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. Furthermore, we propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.

Design of hybrid circuits and systems based on CMOS and nano-device requires rethinking of fundamental circuit analysis to aid design exploration. Conventional circuit analysis with modified nodal analysis (MNA) cannot consider new nano-devices such as memristor together with the traditional CMOS devices. This paper has introduced a new MNA method with magnetic flux (Φ) as new state variable. New SPICE-like circuit simulator is thereby developed for the design of hybrid CMOS and memristor circuits. A number of CMOS and memristor-based designs are explored, such as oscillator, chaotic circuit, programmable logic, analog-learning circuit, and crossbar memory, where their functionality, performance, reliability and power can be efficiently verified by the newly developed simulator. Specifically, one new 3-D-crossbar architecture with diode-added memristor is also proposed to improve integration density and to avoid sneak path during read-write operation.

In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.

Robust, high-performance and low-power match-line sense amplifier designs are urgently required to catch up with the new requirements of large-scale CAMs in nano-scale CMOS technologies. In this paper we evaluate the performance of four state-of-the-art match-line sense amplifier designs in terms of power, delay and robustness against temperature, supply voltage and process variations. Our results show that the pre-charge low match-line sensing schemes suffers from process variations. Despite featuring low power consumption, these designs can hardly be scaled down to operate in low-voltage sub-65 nm CMOS process. On the other hand, the conventional and the charge-injection designs are much more robust and hence more suitable for low-voltage sub-65 nm CMOS implementations.

In a Content Addressable Memory (CAM) architecture, both the match-line (ML) sensing circuit and the priority encoder (PE) contribute significantly large delays during a compare cycle. Meanwhile the priority encoder consumes significantly less energy when compared to the sensing circuits, i.e. ~1% of the overall energy consumption. Based on this observation, we propose the use of dual-supply voltages to trade-off the power and delay budget between the comparison and priority encoding circuits. In this work, the memory array and priority encoder is powered by a low and a high supply voltage, respectively. On top of this, a self-power-off ML sense amplifier is employed to reduce the voltage swing on the ML buses. Simulation results show a 76% dynamic power reduction as compared to the conventional design without sacrificing the overall speed.

A two-stage down-conversion architecture for 3.1–8 GHz ultra-wideband receiver front-end is designed which uses a local oscillator frequency equal to half the input frequency. The down-conversion technique is performed in two steps based on half-RF architecture to produce baseband signal. The proposed technique is implemented in 0.18 µm CMOS technology which achieves a conversion gain ranges from 36.1–32.4 dB and noise figure of 5.4–8.3 dB across the bandwidth.

In this paper, we reported an adaptive priority toggle asynchronous tree arbiter for Address Event Representation (AER)-based image sensors. Simultaneous requests from event-triggered pixels, event latency, timing error and jitter are the inherent issues in AER-based read-out circuits. Fixed priority arbiter often results in unfair allocation of bus resource to only “privileged” pixels thus resulting in timing error. The proposed arbiter is able to reduce the timing error by toggling the requests priority during simultaneous requests. This also achieves the fair allocation of bus resource to all pixels. The featured eager propagation scheme allows the requests to propagate towards higher hierarchy in the tree during the arbitration process. As a result, latency and jitter problems can be reduced. Simulation result reveals that single event delay for 128-way tree arbiter is 4.2 ns and therefore, for 128 × 128 array, such arbiter can process up to 238.09M event/s which is more than 15 times faster than the speed of the reported AER sensor. The arbiter layout was realized with 2P4M 0.35µm CMOS process with a silicon area of 78 × 18µm2and had been implemented in 80 × 80 array AER temporal contrast sensor.

A new current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bit- and data-line capacitances. Extensive post-layout simulations, based on an industry standard 1 V/65-nm CMOS technology, have verified that the new design outperforms other designs in comparison by at least 27% in terms of speed and 30% in terms of power consumption. Sensitivity analysis has proven that the new design offers the best reliability with the smallest standard deviation and bit-error-rate (BER). Four 32 × 32-bit SRAM macros have been used to validate the proposed design, in comparison with three other circuit topologies. The new design can operate at a maximum frequency of 1.25 GHz at 1 V supply voltage and a minimum supply voltage of 0.2 V. These attributes of the proposed circuit make it a wise choice for contemporary high-complexity systems where reliability and power consumption are of major concerns.

A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.

A novel passive mixer architecture is proposed which uses a voltage-mode passive mixer with a tuned output pole. Using this technique, it is shown that the IF section's IIP3requirements are relaxed by up to 33 dB for the IEEE 802.15.4 standard. This allows for use of an ultralow power IF section without linearity compensation. The overall receiver front end consisting of an LNA, a mixer and a third-order channel-select filter is designed in 0.18 µm CMOS technology with a 1-V supply voltage, and post-layout simulations show a 5 dB NF with only 1.7-mW total power consumption.

This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15.4 frequency sysnthesizer designed using 0.18 µm CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and 6 bit P and S counters to provide the 1MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 µW. The S-QVCO consumes 2.8 mW of power with a phase noise of −122.4 dBc/Hz at 1MHz offset.

In this paper, a novel current-mode transimpedance amplifier (TIA) exploiting the common gate input stage with common source active feedback has been realized in CHRT 0.18 ¿m -1.8 V RFCMOS technology. The proposed active feedback TIA input stage is able to achieve a low input impedance similar to that of the well-known regulated cascode (RGC) topology. The proposed TIA also employs series inductive peaking and capacitive degeneration techniques to enhance the bandwidth and the gain. The measured transimpedance gain is 54.6 dB¿ with a -3 dB bandwidth of about 7 GHz for a total input parasitic capacitance of 0.3 pF. The measured average input referred noise current spectral density is about 17.5 pA/¿{Hz} up to 7 GHz. The measured group delay is within 65 ± 10 ps over the bandwidth of interest. The chip consumes 18.6 mW DC power from a single 1.8 V supply. The mathematical analysis of the proposed TIA is presented together with a detailed noise analysis based on the van der Ziel MOSFET noise model. The effect of the induced gate noise in a broadband TIA is included.

In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.

A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empirical expressions. Thus, the proposed model can be easily incorporated with commercial electronic design automation (EDA) tools. The accuracy of the model is validated by the on-wafer measurements up to 20 GHz.

This paper presents the design of a high-speed CMOS sample-and-hold (S/H) circuit for pipelined analog-to-digital converters (ADCs). This S/H circuit employs a conventional switched-capacitor (SC) S/H and a built-in comparator to generate the mixed-mode sampled data output (which is represented both in analog and digital formation). Due to the mixed-mode sample-and-hold technique, this S/H circuit has a reduced output signal swing thus improves the speed and linearity compared to conventional S/H circuits. The aperture errors at high frequency are minimized by using time constants matching and digital error correction logic in pipelined ADCs. Designed in a 0.18mum CMOS technology, the proposed S/H circuit operates up to 200-MHz sampling with less than -53dB total harmonic distortion (THD) in the worst case corner simulation. The power consumption is less than 3.6-mW with 1.8-V supply voltage

A new time variant model for the time domain jitter in the TSPC frequency divider is proposed. The trade-off between the phase noise and power consumption in the prescaler design is analyzed. Based on the analysis, a new prescaler that has a better balance among the operating frequency, power consumption and phase noise is proposed. The analysis is verified by the simulation and measured results in this prescaler

This paper investigates the properties of the on-wafer interconnects built in a 0.18-/spl mu/m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated.

The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW power consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low power consumption for 5-6-GHz wireless LAN applications.