Modern real-time embedded systems increasingly use runtime reconfigurable architectures to reduce size, weight, and power while ensuring predictability. However, reconfiguration delay is non-negligible and varies due to resource contention. Unlike existing solutions that affect system resources or timing, this paper presents an approach and tools to provide a safe, tight reconfiguration delay bound by accurately modeling contention, without additional resource usage, and applicable to most embedded Systems-on-Chip. Additionally, by using Quality-of-Service mechanisms available in modern systems-on-chip, the proposed approach allows designers to set an upper limit for the reconfiguration delay and maintain it against interference from competing tasks. To evaluate the proposed approach, we present two experiments in which it is applied to a representative configuration on a Xilinx Zynq UltraScale+ platform. Experimental results indicate that the reconfiguration delay bound holds under induced worst-case interference scenarios, ensuring that, under heavy workload conditions, the reconfiguration delay can be up to 6.3 times its value in isolation. Moreover, the approach can automatically generate a quality-of-service configuration that ensures a maximum reconfiguration delay 1.8 times its value in isolation, with only a 14% slowdown on contenders and no additional resource consumption, outperforming the existing state of the art. • An approach to emulate worst-case contention for Dynamic-Partial Reconfiguration. • A tool to inject traffic and characterize Dynamic Partial Reconfiguration delay. • QoS-based mitigation ensuring timing isolation for Dynamic Partial Reconfiguration.

As embedded systems are required to satisfy increasing functional and non-functional requirements, heterogeneous systems-on-chip architectures are progressively adopted. While these complex systems-on-chip deliver high performance, they require efficient coordination of the tasks they carry out. To tackle this challenge, designers often resort to runtime mechanisms allowing the dynamic alignment of application requirements with platform services. In turn, runtime mechanisms require the adoption of on-chip monitoring systems. The integration of on-chip monitoring systems into a system-on-chip results in a monitored system-on-chip. Notwithstanding, this integration risks driving a re-design and a re-implementation of the whole system-on-chip, potentially driving to a time-to-market deadline miss. In the literature, HW/SW co-design approaches for monitored systems-on-chip have been proposed to overcome the problem. However, the existing HW/SW co-design approaches prevent performing a system-level design-space exploration that involves all the monitoring requirements, and they also prevent adequate reuse of existing on-chip monitoring systems. This article proposes an approach for efficient HW/SW co-design of monitored systems-on-chip, aiming to comprehensively capture all monitoring requirements at the system-level and to perform a system-level design-space exploration to satisfy them, enforcing the reuse of existing on-chip monitoring systems. The proposed approach is validated through two experimental activities, which demonstrate a 24% reduction in total development time for a monitored system-on-chip implemented on FPGA, compared to the customary approach. The results also show that the approach reduces the risk of missing time-to-market deadlines, supports flexible design choices, and enables the reuse of on-chip monitoring systems.

Commercial embedded systems increasingly rely on heterogeneous architectures that integrate general-purpose, multi-core processors, and various hardware accelerators on the same chip. This provides the high performance required by modern applications at a low cost and low power consumption, but at the same time poses new challenges. Hardware resource sharing at various levels, and in particular at the main memory controller level, results in slower execution time for the application tasks, ultimately making the system unpredictable from the point of view of timing. To enable the adoption of heterogeneous systems-on-chip (System on Chips (SoCs)) in the domain of timing-critical applications several hardware and software approaches have been proposed, bandwidth regulation based on monitoring and throttling being one of the most widely adopted. Existing solutions, however, are either too coarse-grained, limiting the control over computing engines activities, or strongly platform-dependent, addressing the problem only for specific SoCs. This article proposes an innovative approach that can accurately control main memory bandwidth usage in FPGA-based heterogeneous SoCs. In particular, it controls system bandwidth by connecting a runtime bandwidth regulation component to FPGA-based accelerators. Our solution offers dynamically configurable, fine-grained bandwidth regulation – to adapt to the varying requirements of the application over time – at a very low overhead. Furthermore, it is entirely platform-independent, capable of integration with any FPGA-based accelerator. Developed at the register-transfer level using a reference SoC platform, it is designed for easy compatibility with any FPGA-based SoC. Experimental results conducted on the Xilinx Zynq UltraScale+ platform demonstrate that our approach (i) is more than$100\times$faster than loosely-coupled, software controlled regulators; (ii) is capable of exploiting the system bandwidth 28.7% more efficiently than tightly-coupled hardware regulators (e.g., ARM CoreLink QoS-400, where available); (iii) enables task co-scheduling solutions not feasible with state-of-the-art bandwidth regulation methods.

The cybersecurity domain faces a critical disparity between the escalating demand for skilled professionals and the limited talent pool. This gap is primarily driven by the surge in cyberattacks perpetrated by malicious actors seeking financial gain or disruption. These attacks, encompassing tactics like Distributed Denial-of-Service (DDoS) and ransomware, pose significant threats to data security and public safety. To bridge this gap, several challenges must be addressed. We need to prioritize initiatives that enhance people’s awareness and education in cybersecurity. Additionally, exploring innovative training methods and leveraging technology to equip cybersecurity professionals with the necessary skillsets is crucial.

This demo paper presents the VirtuOR multidisciplinary project aiming at leveraging Immersive Virtual Reality for pain management in operative rooms. Addressing the limitations of existing literature, the project proposes an ontology-based framework for designing Immersive Virtual Environments and setting them by anaesthetists. The framework’s key features are discussed, and its practical application is shown through a prototype tailored for patients undergoing specific surgical procedures in operative rooms.

This paper introduces SeriousGXcraft, an innovative XML-based framework for the development of serious games (i.e., their design, implementation, and evaluation). This framework overcomes the limitations of existing ones by leveraging the flexibility of XML and providing a comprehensive and integrated solution. It promotes multidisciplinary collaboration and ensures a harmonious balance between the playful and educational aspects of serious games. By harnessing the capabilities of XML schema, which describes elements related to the target audience, abstract level, concrete level, and actual level, SeriousGXcraft empowers the development team to effectively browse and provide visual support for the complex facets of the serious game development process.

The objective of the FRACTAL project is to create a novel approach to reliable edge computing. The FRACTAL computing node will be the building block of scalable Internet of Things (from Low Computing to High Computing Edge Nodes). The node will also have the capability of learning how to improve its performance against the uncertainty of the environment. In such a context, this paper presents in detail one of the key use cases: an Internet-of-Things solution, represented by intelligent totems for advertisement and wayfinding services, within advanced ICT-based shopping malls conceived as a sentient space. The paper outlines the reference scenario and provides an overview of the architecture and the functionality of the demonstrator, as well as a roadmap for its development and evaluation.

Nowadays, complex Cyber-Physical Systems (CPSs) often exploit the so-called computing at the edge (i.e., edge-computing), where the Dynamic Partial Reconfiguration (DPR, also known as Dynamic Function eXchange or Partial Reconfiguration) feature has been proved to be efficient to face the adaptivity challenges typical of the CPSs domain. In this context, the increase of both platforms heterogeneity and required customizations are leading to a growth of the number of per-task requested DPR, for which Industry is enhancing the reconfiguration controllers providing the capability to offload more than one DPR request, in turn allowing pipelining between multiple DPR processes and application execution. Several works in literature have introduced the DPR process in the hard real-time system domain, however not considering the multiple DPR offloading capabilities. In this paper, we provide a theoretical analysis and a practical evaluation of multiple DPR offloading in the context of hard real-time systems. In particular, through a motivational case-study, supported by some experimental activities conducted on the Zynq-7000 SoC, we show how the offload of multiple DPR can provide benefits with respect to the traditional approach of one DPR request per time.

Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.

The objective of the FRACTAL project is to create a new approach to reliable edge computing. The computing node will be the building block of scalable Internet of Things (from Low Computing to High Computing Edge Nodes). The cognitive skill will be given by an internal and external architecture that allows forecasting its internal performance and the state of the surrounding world. The node will have the capability of learning how to improve its performance against the uncertainty of the environment. New industrial functions will flourish through the created space of the cognitive system. Cognitive advantages are brought to a resilient edge and a computing paradigm that lay down between the physical world and the cloud.

Nowadays, circa 10% of 7-11 olds turn out to be poor comprehenders: they demonstrate text comprehension difficulties, related to inference making, despite proficiency in low-level cognitive skills like word reading. To improve the reading comprehension of these children, TERENCE, a technology enhanced learning project, aims at stimulating inference-making about stories. In order to design and develop the TERENCE system, we use a user centred design approach that requires an in depth study of the system's main end-users, namely, its learners and educators. This paper reports on the specification of the user classes for the TERENCE learners by means of user-centred design field studies, the resulting global system architecture, and an example use case of the system, with few related GUI's snapshots.

Our intent is to validate the adoption of an enclosure-based visualization technique of hierarchical structures for the presentation of web sites, according to a paradigm that (1) abandons the concept of web page collection and (2) replaces the link-traversal based navigation with a zoom-based navigation. In particular we re-visit the box-in-box technique (originally introduced to visualize objects in a knowledge base), based on recursive containment among labeled boxes, where panning and zooming operations allow to move the visibility window over the structure. The paper presents the main features of web sites, sketches system characteristics and architecture, and discusses results of a preliminary evaluation study based on the comparison between a traditional version and a boxed version of the same site.

This paper presents a system supporting tuning and evaluation of a Content-Based Image Retrieval (CBIR) engine for vector images, by a graphical interface providing query-by-sketch and query-by-example interaction with query results, and analysis of result quality. Vector images are first modelled as an inertial system and then they are associated with descriptors representing visual features invariant to affine transformation. To support requirements of different application domains, the engine offers a variety of moment sets as well as difierent metrics for similarity computation. The graphical interface offers tools that helps in the selection of criteria and parameters necessary to tune the system to a specific application domain.