Demo Data from EDBT 2026 / reviewers in the wild / expert
Y. T. Chiang
dblp:51/8530
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1984
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 50% Integrated circuit design · 50% | |
| Artificial intelligence
1 paper |
Image recognition and object detection · 100% | |
| Theoretical computer science
1 paper |
Automata and formal languages · 100% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › VLSI design
VLSI array |
0.0 | 1 | 1984 | Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition · IEEE Trans. Pattern Anal. Mach. Intell. 1984 |
Computer vision › Image recognition and object detection › structural pattern recognition
syntactic pattern recognition |
0.0 | 1 | 1984 | Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition · IEEE Trans. Pattern Anal. Mach. Intell. 1984 |
Automata and formal languages › parsing
context-free grammar parsing |
0.0 | 1 | 1984 | Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition · IEEE Trans. Pattern Anal. Mach. Intell. 1984 |
Methods — techniques the papers use, named apart from their topics
error-correcting parsing · 0.0earley's algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1984 | Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern RecognitionabstractEarley's algorithm has been commonly used for the parsing of general context-free languages and the error-correcting parsing in syntactic pattern recognition. The time complexity for parsing is 0(n3). This paper presents a parallel Earley's recognition algorithm in terms of an ``X*'' operator. By restricting the input context-free grammar to be ¿-free, the parallel algorithm can be executed on a triangular-shape VLSI array. This array system has an efficient way of moving data to the right place at the right time. Simulation results show that this system can recognize a string with length n in 2n + 1 system time. We also present a parallel parse-extraction algorithm, a complete parsing algorithm, and an error-correcting recognition algorithm. The parallel complete parsing algorithm has been simulated on a processor array which is similar to the triangular VLSI array. For an input string of length n the processor array will give the correct right-parse at system time 2n + 1 if the string is accepted. The error-correcting recognition algorithm has also been simulated on a triangular VLSI array. This array recognizes an erroneous string of length n in time 2n + 1 and gives the correct error count. These parallel algorithms are especially useful for syntactic pattern recognition. Y. T. Chiang, King-Sun Fu |
IEEE Trans. Pattern Anal. Mach. Intell. | 1 |