The research introduces an innovative seven-level inverter design featuring 24 switches, all powered by a single DC source. The topology of this inverter offers benefits in terms of sensor-less capacitor balancing fault tolerance, and increased DC bus utilization with extended linear modulation range till full base speed. In this paper, the balancing of capacitor voltages relies solely on measuring their voltage, eliminating the need for additional current sensors. The capacitor balancing focuses on minimizing the dependencies on current sensors to determine the direction of capacitor currents. By using these measured values, logical variables and equations are created. These logical expressions remain effective across linear and extended linear modulation ranges, eliminating all lower-order harmonics.The modulation technique used is space vector pulse width modulation (SVPWM). The simulation results show how well a state-of-the-art seven-level inverter can operate an induction motor (IM) drive.

The paper proposes a low switch count multilevel inverter topology having a four-level space vector structure. The proposed MLI demonstrates a reduced number of active switches in relation to the number of output voltage levels. This inverter has an increased DC bus utilization, reaching up to 0.637 times the DC link voltage compared to the conventional multilevel inverters limited to 0.577 times the DC link voltage.The proposed multilevel inverter configuration integrates a two-level inverter with a cascaded H-bridge (CHB) converter in each phase. The each CHB capacitor voltage are regulated to one third of dc link voltage. The enhanced utilization of the DC bus voltage is due to the space vector redundancies provided by the CHB units. Both simulation and experimental validation of the proposed scheme are conducted on an induction motor drive across for various operating conditions. Field-oriented control (FOC) is employed to control the speed of the induction machine, while examining capacitor balancing under various transient conditions.

An X-ray medical apparatus requires a high voltage to operate and shall be produced from a domestic 3-phase or 1-phase AC supply in hospitals. Along with this comes a power quality issue, as this medical device has become common. Following a typical X-ray datasheet, the voltage level must increase from 400/415 volts mains to 120 kV. Due to the above reason, several stages are required to boost the voltage level to the required level. This leads to the heavy size of the equipment, increased losses, and poor power quality. This paper proposes a methodology to implement the power supply generator circuit for an X-ray device that adopts 1) a 3-phase Boost PFC (Power Factor Correction) rectifier, 2) a High-frequency series resonant inverter, and 3) a Voltage multiplier circuit. ZCS (Zero Current Switching) has been adopted to reduce switching losses due to high-frequency switching frequency.

A conventional inverter-based induction motor drive has a maximum peak fundamental phase voltage of 0.577V dc, corresponding to a peak voltage space vector radius of 0.866V dc in its linear modulation range. The magnitude 0.866V dc here correlates to the radius of the largest circle that can be inscribed in the hexagonal space vector structure created by the inverter. Beyond 0.866V dc lies the overmodulation region where the inverter operates in a six-step mode. Here the voltage space vector traces a hexagonal locus causing a lower order harmonic rich phase voltage. In the proposed inverter scheme, the linear modulation range can be extended till a maximum peak phase fundamental voltage of 0.637V dc while achieving a circular trajectory of radius 0.955V dc for the voltage space vector, thus eliminating all lower-order harmonics. This extends the linear modulation range to the full base speed of the induction motor.

In this paper, DC-link capacitors voltage deviation control is achieved using a symmetrical six-phase induction machine (IM) load driven by a nine-level inverter. The motor phase currents are utilised intelligently to control the common coupling points (CCPs: terminal connections series-connected capacitors across a DC-link). Each phase of this inverter consists of a five-level stacked inverter and two cascaded H-bridge (CHB) inverters, which can be built using low voltage switching devices. Simultaneous control of DC-link capacitors and CHB capacitors balancing is achieved by using the pole voltage redundancies. This concept is validated using a standard simulation tool with a six-phase load under the 'V/f' control operation. The simulation results for steady-state and transient conditions are provided at low speed and high speed of operation with low and high power factors conditions. © 2022 IEEE.

The high-voltage and high-power applications require isolated systems to maintain safety. Also, the existing power semiconductor devices limit the maximum operating range. This paper presented an integrated magnetics-based flux-rate controlled single-phase inverter topology to achieve the isolation and enhance the maximum operational capacity with the current power semiconductor devices. The proposed inverter topology is comprised of the main and secondary inverter and the integrated magnetic circuit. The high-power main inverter performs the fundamental frequency operation throughout the entire operating range, which is responsible for setting up the main flux in the magnetic core. The low power secondary inverter performs high-frequency PWM (pulse width modulation) operation and sets up the required flux rate in the magnetic core. The flux-rate control in the magnetic circuit makes the output voltage waveform sinusoidal across the load terminals. Proper arrangement of the load winding of the magnetic circuit takes care of the isolation and makes the load-side free from power electronics components. The graphical modeling technique bond-graph is used here to model the proposed system. The obtained model is simulated, and the experimentation is performed on a lab-built prototype to demonstrate the functioning of the proposed inverter. © 2022 IEEE.

In this paper, an electromagnet rotor based switched reluctance machine (ESRM) is proposed for electric vehicle (EV) applications. The proposed machine is realized with the winding on the rotor. Because of these rotor winding, higher torque density (Nm/kg), reduced input current, wider-torque speed characteristics are achieved. This is done by establishing rotor excitation through innovative power transfer from stator to rotor or extracting power from space harmonics. In the first approach of rotor excitation through wireless power transfer (WPT) system, the stator has transmitting coil fed by resonant converter and the rotor has receiving coil which has high pass filter to allow high frequency signals necessary for rotor excitation. A 50kW ESRM has been modelled and validated in FEM (Finite Element Method) simulations tools like FEMM and JMAG.

A multi-level inverter circuit for generation of a dense multilevel 24-sided polygonal voltage space vector structure (VSVS) with real active vectors is proposed in this paper for open-end winding configuration induction motor (OEIM) drive. Generation of real active vectors compared to the switched average vectors, reduces switching frequency and improves phase voltage quality. Dense structure allows to generate 24-stepped output voltage waveform in full speed range with approximately 2Hz resolution. Due to 24-stepped waveform, output voltage is free from lower order harmonics upto 19th order in full speed range. The proposed inverter consists of inverter-1 and inverter-2, feeding from both the ends of the motor. The DC sources for the inverter scheme are generated by using simple delta-star-delta transformer connections while providing isolation from the grid. Capacitors in the power circuit are balanced using pole voltage redundancies without employing any extra circuit. The effectiveness of the proposed scheme is verified using MATLAB simulation and results are in agreement with the proposed theory. © 2022 IEEE.

The Induction Motor Drives based on polygonal voltage space vector structures proposed in literature make use of switched-capacitive filtering for the suppression of lower order harmonics in the motor phase voltage. The Open-End Induction Motor (OEIM) drive systems feed the Motor with a primary and secondary inverter from either end. The primary inverter is fed with an active DC link supply, that provides all the active power for motor operation. The harmonics in motor phase voltage generated by primary inverter, are suppressed by employing a secondary inverter fed with a capacitive supply. The superposition of primary and secondary vectors generate reference vectors, that lie on the tips of a regular polygon. This work explains explains the suppression of lower order harmonics by Polygonal Voltage Space Vector Structures, by proposing a method of visualizing the harmonics in the α − β plane. The cancellation of fifth and seventh order harmonics in the reference space vector for a 42- sided Voltage Space Vector Structure will be explained using the proposed method of visualizing the harmonics. The 5thand 7thorder harmonics are canceled, as the reference vector spans a 60° duration. The suppression of said harmonics by secondary inverter, results in sixth harmonic reactive power in secondary inverter. A quantitative analysis is carried out for the design of capacitor feeding secondary inverter to maintain a small ripple in secondary inverter, while delivering sixth order power for suppression of harmonics.

A 21-concentric 42-sided polygonal space vector structure (SVS) for suppression of lower order harmonics for Open-End Induction Motor drive applications is proposed in this work. The Open-End Induction Motor is fed with primary and secondary inverters from either side. The primary inverter providing active power for motor operation is fed with an active DC link. The primary inverter is switched at low switching frequency to minimize stress on high voltage switching devices. As a result, the primary inverter consists of lower order harmonics in the pole voltage. The secondary inverter is employed only to suppress the harmonics generated by primary inverter and does not contribute any active power for motoring operation. Hence, the secondary inverter can be fed with a capacitive supply balanced at a nominal voltage. The secondary inverter, operating at lower voltages is switched with high frequency to suppress the lower order harmonics upto 39thorder in the motor phase voltage. The advantages of polygonal space vector structures are retained throughout the modulation index, by generating 21-concentric layers of 42-sided polygons. This results in lower switching losses in low frequency switching main inverter and low voltage secondary inverter. A single DC link is employed in the power circuit topology to facilitate four-quadrant operation of the inverter. The proposed scheme is tested in MATLAB simulations and laboratory prototype. The simulation and experimental results are presented.

This paper proposes a new power circuit topology to generate a 24-sided polygonal voltage space vector structure(SVS) for elimination of lower order harmonics up to 19thorder from motor phase voltage through out the modulation range. Generated space vectors are realized without switched average technique minimizing switching losses. In the proposed scheme, an open end winding induction motor is fed with a primary inverter from one end and a secondary inverter from the other end. The primary inverter and secondary inverter are implemented using combination of cascaded 2 level inverters. The dc power sources required are such that they are easy to generate using star delta transformer connections. The machine phase voltage is devoid of all the lower order harmonics (5th, 7th, 11th, 13th,17th, 19th) which gives sinusoidal phase current and smoother torque profile for motor operation. The proposed scheme extends the linear modulation range till 99.42%. The proposed scheme is implemented and verified with MATLAB simulation and validated with experimental results.

This paper proposes the generation of a multilevel 30-sided space vector structure (SVS) from a single DC-link for an open-end induction motor (OEIM) drive. This scheme exhibits the inherent advantages of multilevel inverters like usage of low voltage blocking switches, less dv/dt in phase voltage etc. As the SVS generated is a 30-sided, lower order harmonics till 25thorder is eliminated from the motor phase voltage. Linear modulation range is also extended till 99.63% of the base speed as the SVS is closer to a circle. The topology consists of a DC-link fed hybrid 5-level inverter feeding one end of the OEIM and a capacitor fed hybrid 5-level inverter feeding from the other end of the OEIM. Active DC-link fed inverter acts as the only source of active power while the inverter feeding from the other end acts as a switched harmonic filter. Simulation studies and experimental verification of the proposed scheme are performed and presented in this paper.

In this paper, the method to extend linear modulation range till full base speed irrespective of the load power factor (p.f.) is presented using a 5-Level inverter scheme. Using this method, inverter can be operated linearly till peak phase fundamental voltage of 0.637Vdc(i.e. till full base speed) without exceeding machine phase voltage rating. The 5-level inverter is realized by a dual-fed inverter scheme for Open-End Induction Motor (OEIM) drive. A 2-Level inverter cascaded with a H-Bridge inverter acts as primary inverter and feeds the drive from one end whereas capacitor fed 2-Level inverter acts as secondary inverter and feeds the drive from another end. A single DC source is connected with primary 2-Level inverter. The ratio of the DC-link voltage to the primary H- Bridge inverter capacitor voltage is 4:1 and the DC-link to the secondary inverter capacitor voltage is maintained at 2:1 ratio for proper 5-Level inverter operation. Simulation and experimental results for inverter operation till full base speed are presented in this paper for OEIM and resistive load under steady state and dynamic conditions.

Multilevel higher-sided polygonal (more than six sides) voltage space vector structures are becoming a forefront choice for obtaining high quality low distortion output voltages for variable speed drive applications. Unique class of multilevel inverter topologies generating polygonal voltage space vector structures have advantages - full DC bus utilization, low-order harmonic suppression in output voltage for entire speed range operation with low switching frequency strategies, and extended linear modulation range as near to the base speed, apart from other advantages of multilevel inverters. In this paper, generation of a high density multilevel (13-level) polygonal space vector structure with 24-sides using a single DC source is presented. The realization of space vector structure is discussed, performance of the drive scheme during steady state and transients are extensively studied through simulation and are validated through experiment.

This paper proposes a hybrid 7-level inverter scheme formed by cascading basic inverter cells. The proposed inverter is realized by cascading basic 3-level T-type converter with 5-level active neutral point clamped inverter. The proposed topology uses low voltage semiconductor devices and floating capacitors which are balanced in every PWM switching cycle using pole voltage redundancies for every pole voltage levels. The balancing of capacitors are independent of modulation index and load power factor. The topology forms two stacks at the front-end which uses individual symmetrical reduced DC sources and each stack works only for half the fundamental period. The open loop V/f control is simulated as well as experimentally verified on induction machine using proposed inverter topology. The experimental and simulation results for transient and steady state operations are included in the paper. Further, a brief comparison of proposed topology with conventional 7-level topologies have also been included.

Dodecagonal (12-sided polygon) voltage space vector structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lower switching frequency requirement - making it more suitable for high power drive applications. A simple carrier based modulation method is proposed to obtain space vector pulse width modulation (SVPWM) switching patterns for a dodecagonal voltage space vector (SV) structure using only sampled reference voltages in this paper. The algorithm outputs the sector information and the SVPWM compare values which can be set as the references for any PWM module to obtain SVPWM switching sequences. The proposed method eliminates the need for partitioning and recombination of the computed timing values, angle estimation and computation of modulation index which in common in conventional SVPWM modulation technique. Simulation and experimental results are presented to validate the proposed method.

This paper proposes an induction motor drive scheme generating multilevel twenty-four sided voltage space vector structure using single DC source. The topology consists of basic units with DC-source fed main three-level flying-capacitor (FC) inverter cascaded with two low-voltage floating-capacitor fed H-Bridge cells (CHB). The generated space vector structure has six concentric 24-sided polygons. The CHBs are modular and independent in operation performing low voltage switched filtering action canceling dominant low-order harmonics generated by the main inverter. Linear modulation index as close to base speed is achieved with 24-sided structure. Single DC source based topology allows four quadrant operation of drive system simpler. Modulation scheme with minimum switching operation for FC inverter is verified. Simulation results under steady state and transient operations for V/f scheme are presented in the paper and validated through experiment.

This paper presents a seventeen level inverter topology for open end induction motor drives requiring only twelve switches per phase. One three-level inverter and one seven-level inverter with DC link voltages in 3∶1 ratio are connected to the two ends of the stator winding of the induction motor to generate a seventeen level space vector structure. A level shifted carrier based scheme is used to modulate the inverter, which requires only instantaneous phase voltage references. Selection of switching states is used to ensure that both inverters supply real power to the motor the over entire modulation range, preventing overcharging of the DC bus. The topology was tested for steady state operation over the entire modulation range, and experimental results are included below.

This paper proposes a new forty nine level stacked inverter topology using low voltage devices for drives applications. The forty nine level inverter is developed by stacking three seventeen level inverters. The seventeen level inverter is developed by cascading a flying capacitor inverter and three H-Bridges. The inverter can operate with lower number of voltage levels if any of the H-Bridges fail. The capacitor voltage balancing in the inverter can be done irrespective of modulation index and load power factor. The topology is further modified to reduce the capacitor and switch count. Also, the inverter does not use any pulse width modulation between the different voltage levels. Therefore switching losses are reduced. In addition, since the switches need to block only lower voltages, MOSFETs can be used which will further improve the efficiency. An induction motor driven by this inverter using V/f control is simulated in MATLAB simulink and both steady state and transient results are presented.

A method to obtain pulse width modulation (PWM) timings for a three level dodecagonal (12-sided polygon) voltage space vector structure using only sampled reference values is proposed in this paper. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle to get the timings by using trigonometric calculations. This method requires look-up tables, angle estimation making it difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle within a sector. The proposed method does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. It is also is generic and can be extended to any number of levels with symmetric structures. The algorithm outputs the triangle number and the PWM compare values - that can be used by any carrier based PWM module to obtain space vector PWM like switching sequences. Extensive simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method.

This paper presents a nine level inverter topology with only eight switches per phase, for driving an induction motor with open end stator winding. The topology consists of two three-level, three phase inverters connected to the two ends of the induction motor. With asymmetric DC link voltages in a ratio of 3:1, an effective nine level space vector structure is realised. Modulation is done using level shifted carriers, which requires only sampled values of the three phase voltage references. Switching state redundancies are used effectively to ensure that both inverters supply real power to the load over the entire modulation range preventing overcharging of the DC links. In case of a fault in one of the inverters, the faulty inverter can by bypassed and operation is possible using the other inverter. The topology was simulated using MATLAB/Simulink and experimentally verified over the entire linear modulation range. Experimental results validating the proposed scheme are included.

In this paper, a nineteen level dodecagonal voltage space vector structure is proposed for the first time, by cascading two asymmetric three level inverters with isolated H-Bridges. The dodecagonal structure is made possible by proper selection of DC link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of dodecagonal voltage space vector structure. A generic and simple method for calculation of PWM timings is proposed. Also, a new method of switching technique is proposed, which ensures minimum switching while maintaining the linearity between modulating signals and the output phase voltages. Extensive simulation and experimental results have been presented for validation of the proposed concept.

Voltage source inverter (VSI) fed six-phase induction motor drives have high 6n ± 1; n = odd order harmonic currents, due to absence of back emf for these currents. To suppress these harmonic currents, either bulky inductive harmonic filters or complex pulse width modulation (PWM) techniques have to be used. This paper proposes a simple harmonic elimination scheme using capacitor fed inverters, for an asymmetrical six-phase induction motor VSI fed drive. Two three phase inverters fed from a single capacitor is used on the open-end side of the motor, to suppress 6n ± 1; n = odd order harmonics. A PWM scheme that can suppress the harmonics, as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected. The proposed scheme is verified using MATLAB Simulink simulation at different speeds. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. Experimental results are also provided to validate the functionality of the proposed controller.

In the present paper, a novel topology for generating a 17-level inverter using three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors. The proposed circuit is analyzed and various aspects of it are presented in the paper. This circuit is experimentally verified and the results are shown. The stability of the capacitor balancing algorithm has been verified during sudden acceleration. This circuit has many pole voltage redundancies. This circuit has an advantage of balancing all the capacitor voltages instantaneously by switching through the redundancies. Another advantage of this topology is its ability to generate all the 17 pole voltages from a single DC link which enables back to back converter operation. Also, the proposed inverter can be operated at all load power factors and modulation indices. Another advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels.

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18 sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three level inverters. By proper selection of DC link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector based PWM techniques are the complete elimination of fifth, seventh, eleventh and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Matlab simulation results and experimental results have been presented in this paper to validate the proposed concept.