This paper analyses the sensitivity of the pMOS Wheatstone bridge stress sensors in 180-nm CMOS process. Other reported works use coarser process nodes. The pMOS sensors have a maximum or minimum sensitivity to the in-plane normal stress components for different orientations of the bridge arms with respect to the wafer coordinate system. The experimental results show that the sensors oriented orthogonally to the wafer axes have an absolute sensitivity of around 400 µV/MPa, while the absolute sensitivity of the diagonally oriented sensors is around 3 µV/MPa. The temperature measurements show low temperature dependency. The sensitivity to stress changes around −3% at 5 °C and around +1% at 50 °C, with respect to 25 °C.

This paper presents a stress-dependent MOSFET model which is valid from strong to weak inversion, based on the extension of the previous model that covers only the operation in strong inversion. The presented model operates for any MOSFET model type since it does not depend on model parameters. It can be used to simulate complex circuits and compensate for the effects caused by mechanical stress. Mechanical stress is caused by IC packaging and can potentially bring the circuits out of specifications, but stress-aware device models are not standard in circuit simulators which limits the ability to simulate these effects. A measurement method is presented and used to calibrate and validate the models.

In this work, the design methodology of the relaxation oscillator with the post-processing trimming option for frequency and temperature coefficient is presented. A novel oscillator core is introduced, which ensures good control linearity and insensitivity to CMOS variations of the output frequency as a prerequisite for frequency and temperature calibration. The proposed oscillator operates at 2 MHz and consumes typically about$I_{DD}=97.8\,\,\mu \text{A}$at the nominal temperature of 42.5°C and nominal supply voltage of$V_{DD}=1.8$V. The oscillator is verified experimentally with 10 samples manufactured in 180 nm CMOS process, each covering an area of 0.075 mm2. The frequency and temperature calibration was performed based on the two-point temperature measurements, resulting in a significant improvement in frequency stability. The temperature calibrated oscillator has a temperature variation ±0.30% in the temperature range from −40°C to 125°C, and the variation with the power supply ±0.07% in the supply range from 1.62 V to 1.98 V.

A recent paper improved the state of the art for resonant class-E dc/dc converters by relaying their design on the solution of an associated non-linear dimensionless mathematical system. We show in this paper that when the associated nonlinear system can be solved, the solution is not always unique. By considering a simple case study we are able to compute two different solutions leading to two different designs. In the first one the main spectral component of voltage and current waveforms is located around the first clock harmonic, and around the second harmonic in the other solution. Interestingly, the latter design leads to a reduction either in the size of inductors/transformers or in the oscillation frequency (a 2.46× factor), and also a non-negligible improvement in the converter efficiency (from 74.1% to 75.8%).

An improved relaxation oscillator core is designed and fabricated in 0.35-μm CMOS process, occupying the area of 0.032 mm2and consuming around 160 μW while running at 1 MHz. Employing a self-compensating chopped comparator structure, the designed oscillator exhibits the improvement in the frequency stability, at the same time retaining a fast start-up and having a minimal overhead in the power consumption and area. Measured on 9 test chips, the frequency variation against temperature is ±0.26% in the temperature range from -40 to 125 °C, and the line sensitivity is 0.16 %/V with the supply voltage changing from 3.0 to 4.5 V.

A black-box method for modeling the time-domain response of integrated circuits (ICs) based on echo state networks is proposed. The number and value of the input and feedback delays required for modeling nonlinear systems with memory are detected automatically, and the training procedure is very fast and robust. The resulting models can be implemented in any hardware description language. The proposed modeling approach is applied to three test cases that cover a wide range of analog behavior. The achieved accuracy is comparable to the reference modeling method, and, depending on the complexity of the modeled IC, the simulation speed-up factor is in the order between 10 and 100.