We propose a novel architecture of memory controller, called HMC (Heterogeneous Multi-Channel), as an improvement to the previous homogeneous multi-channel memory controller. HMC groups physical DRAM devices into logical sub-ranks with different data bus width, and controls them simultaneously. Employing new proposed memory access algorithm, HMC manages the number of devices involved in a single memory access flexibly, and achieves the best performance/power efficiency. Using four-core multiprogramming workloads, our experimental results show that HMC improves system performance by 27.6% with 24.2% reduction in DRAM power consumption on average.

This paper presents a new memory access scheduler, called FSCM (Fair Service Curve Memory access scheduler), which targets for the objective that provides the highest system throughput. The main idea of reordering memory access requests based on the service curve is borrowed from the literature of packet-switched networks. Different threads have different QoS (Quality-of-Service) requirements, and FSCM assigns each thread a service curve. The service curve gives great adaptability to FSCM in allocating its bandwidth. We evaluate FSCM using multi-threaded applications, and compare it to three previously proposed memory access schedulers. On a four-core CMP running combinations of workloads with a wide range of memory bandwidth and latency requirements, FSCM improves system performance by 16.7% on average, and provides the best fairness to all of the threads.