Advances in deep neural networks (DNNs) and the availability of massive real-world data have enabled superhuman levels of accuracy on many AI tasks and ushered the explosive growth of AI workloads across the spectrum of computing devices. However, their superior accuracy comes at a high computational cost, which necessitates approaches beyond traditional computing paradigms to improve their operational efficiency. Leveraging the application-level insight of error resilience, we demonstrate how approximate computing (AxC) can significantly boost the efficiency of AI platforms and play a pivotal role in the broader adoption of AI-based applications and services. To this end, we present RaPiD, a multi-tera operations per second (TOPS) AI hardware accelerator core (fabricated at 14-nm technology) that we built from the ground-up using AxC techniques across the stack including algorithms, architecture, programmability, and hardware. We highlight the workload-guided systematic explorations of AxC techniques for AI, including custom number representations, quantization/pruning methodologies, mixed-precision architecture design, instruction sets, and compiler technologies with quality programmability, employed in the RaPiD accelerator.

The combination of growth in compute capabilities and availability of large datasets has led to a re-birth of deep learning. Deep Neural Networks (DNNs) have become state-of-the-art in a variety of machine learning tasks spanning domains across vision, speech, and machine translation. Deep Learning (DL) achieves high accuracy in these tasks at the expense of 100s of ExaOps of computation; posing significant challenges to efficient large-scale deployment in both resource-constrained environments and data centers.

An increasing focus on design productivity is shifting microprocessor design to more synthesis-centric design methodologies. Low power design is also rising in importance, even for higher performance server chips. This paper proposes a design methodology capitalizing on the relatively low cost of parallel synthesis job submission for design space exploration. By tailoring the design flow for parallel and iterative design space exploration we attempt to maximize the return on investment (ROI) of design effort. The methodology was applied to the IBM POWER7+™ microprocessor to save power during the second release of the chip. This paper provides an overview of the methodology as well as chip hardware measurements showing power savings.

The time-to-market pressures combined with the immense power reduction design space of VLSI design call for an evaluation of power savings opportunities prior to the investment in design effort. This paper presents an estimation methodology for predicting the power savings of circuit tuning for an industrial chip design project. A comparison between the estimated and actual power savings realized through tuning over 100 macros on the chip validates the accuracy of this estimation methodology.

Channel subthreshold and gate leakage currents are predicted by many to become much more significant in advanced CMOS technologies and are expected to have a substantial impact on logic circuit design strategies. To reduce static power, techniques such as the use of monotonic logic and management of various evaluation and idle modes within logic stages may become important options in circuit optimization. In this paper, we present a general, multilevel model for logic blocks consisting of logic gates that include a wide range of options for static power reduction, in both the domains of topology and timing. Existing circuit techniques are classified within this framework and experiments are presented showing how aspects of performance might vary across this range in a hypothetical technology. The framework also allows exploration of optimal mixing of techniques.

Article Share on Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design Authors: W. Chen IBM T. J. Watson Research Center, Yorktown Heights, NY IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile , W. Hwang IBM T. J. Watson Research Center, Yorktown Heights, NY IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile , P. Kudva IBM T. J. Watson Research Center, Yorktown Heights, NY IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile , G. Gristede IBM T. J. Watson Research Center, Yorktown Heights, NY IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile , S. Kosonocky IBM T. J. Watson Research Center, Yorktown Heights, NY IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile , R. Joshi IBM T. J. Watson Research Center, Yorktown Heights, NY IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 263–266https://doi.org/10.1145/383082.383156Online:06 August 2001Publication History 6citation4,358DownloadsMetricsTotal Citations6Total Downloads4,358Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this paper the results of an experimental comparison of popular pass-transistor logic families in 1.5V, 0.18µm CMOS technology using advanced CAD tools for circuit tuning and simulation are presented. The logic families were compared using an experimental setup designed to clarify the strengths and weaknesses of each family in a relative fashion and evaluate their individual performances under identical operating conditions. An automatic circuit tuner was used to help ensure that the test circuits from each logic family were operating at near optimum performance. It is shown that the Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) logic family is the most robust with respect to an amalgamation of speed, power, area and physical design criteria. The methodology of using hybrid pass-transistor / static CMOS circuit styles is also presented.

An analysis tool is introduced that measures subcircuit coupling and error attenuation in waveform relaxation (WR) circuit simulation algorithms with full dimensionality. Unlike current methods that use heuristics to calculate scalar gains, this method capture all the effects of error attenuation over time and space. An example is provided of how this technique can be used to study the performance of various partitions, schedules, and WR algorithms on a wide range of technologies, including BiCMOS.>