In this paper, we introduce a novel architecture for constructing caches for lookup operations that are used in a variety of network processing applications. The distinguishing feature of the cache is the ability to match on keys that of arbitrary lengths. We show through an FPGA implementation, that the proposed design can speed up lookup operations significantly compared to a software implementation. In conjunction with a network processor, the use of such a cache can greatly improve the response time of lookup intensive applications such as DNS resolution, directory lookup in network storage, and LDAP queries.

In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructure as they serve as a key line of defense in network protection. However, current methods are much too compute intensive and cannot begin to meet the bandwidth requirements of a moderate sized corporate network. Thus, hardware techniques are desired to speed up network processing. This paper introduces a FPGA based signature match processor that can serve as the core of a hardware based NIDS. The signature match processor's key feature is a CAM-based cellular processor architecture that can match strings in an area efficient manner. Using a unique binary tree structure, we are also able to generate priority encoded addresses corresponding to multiple signature matches.