The significant role played by interconnects in determining the speed and chip size of very-large-scale integrated circuits (VLSI) necessitates the development of new processes and tools for almost every device generation. Since such development usually requires lead times of several years, it has become essential to know, several years in advance, the various interconnect parameters for a particular generation. In this paper, a tool for optimizing interconnect parameters is presented. The formulation of an optimization problem that can be solved using standard algorithms is shown to be possible, and the optimization results obtained for future device generations are discussed. These results can be used to construct an interconnect technology roadmap. Last, shortcomings of and possible improvements to existing system-level critical path models are discussed.

This paper investigates substrate noise influence on circuit performance in a variable threshold-voltage scheme (VT scheme) where threshold voltage is dynamically varied by substrate-bias control to reduce active power dissipation. It is experimentally examined that substrate-bias can be controlled stably with very few substrate-contacts. Measured tracking jitter of a delay-locked loop implemented by interconnections in an 8 mm-square gate array does not degrade even when substrate-contacts are removed except for one at every strip of p-sub and n-well: A 2 mm-square discrete cosine transform core processor with no substrate-contact except in its periphery operates at supply voltages from 1.3 V to above 3 V even though it employs small-swing differential dynamic pass-transistor logic. No performance degradation nor latchup is observed in these chips even when 100 k/spl Omega/ resistance is added to the substrate. These experimental results demonstrate noise immunity of the VT scheme, and indicate the possibility that the VT scheme can be applied to existing macro design easily.