This thesis presents an innovative Physically Unclonable Function (PUF) implemented in 600 nm Indium-Gallium-Zinc-Oxide (IGZO) Thin-Film Transistor (TFT) technology, fabri- cated on Flexible Integrated Circuits (FlexICs). The proposed architecture takes advantage of device level randomness to produce distinct and repeatable digital responses by utilizing the intrinsic Threshold Voltage (Vth) variability of IGZO TFTs as a physical entropy source. Oxide TFTs, as opposed to conventional Complementary Metal-Oxide-Semiconductor (CMOS)-based implementations, enable compatibility with low temperature, large area and mechanically flexible substrates. This approach is particularly well suited for the next generation of Internet of Things (IoT) and wearable electronic systems. The circuit architecture is based on a differential current comparison mechanism, where two transistor arrays are sequentially evaluated and their discharge characteristics are compared to produce a digital output. Cadence Virtuoso transient simulations were statistically modeled using the experimentally extracted Vth distributions from manu- factured IGZO TFT matrices. This allowed for precise analysis of entropy quality and robustness. Nine National Institute of Standards and Technology (NIST) SP 800-22 statis- tical test suites were successfully passed by the resultant bitstreams, demonstrating high entropy and consistent randomness across several simulated instances. Additionally, transient noise simulations were performed to assess stability under process and environmental fluctuations. The bitstream demonstrated a Bit Error Ratio (BER) below 0.4% at the optimal comparator threshold. Overall, the proposed IGZO-TFT PUF demonstrates that thin-film oxide electronics can serve as a foundation for intrinsic, low cost and hardware-based security primitives, suitable for secure identification in flexible and large area electronic systems.

1Three Digital Operational Transconductance Amplifier (DIGOTA) topologies, i.e. the standard DIGOTA, a Schmitt-Trigger-Based DIGOTA (ST-DIGOTA) and a DIGOTA with a Floating-Inverter input stage (FI-DIGOTA), are designed for the first time in a 16nm CMOS FinFET technology and their performance is compared on basis of post-layout simulations. All the DIGOTAs operate at 300 mV power supply while driving a capacitive load of 350 pF. The standard DIGOTA presented the lowest silicon area (44 μm2) and a power consumption of 99.4 nW at 59 kHz Gain-Bandwidth Product (GBW). The ST-DIGOTA achieved the highest DC gain of 43.9 dB, at the cost of a 6X increased power (609 nW) and 14% larger area, while the FI-DIGOTA achieves the highest GBW (100.3 kHz) and Slew Rate (8 mV/μs) at 36X more power (3.67 μW) and 2.5x larger are than the standard DIGOTA.According to these results, an area-normalized large signal figure of merit (IFOMLA) of 117k, 19.2k and 1.8k (mV/μs)•pF/(nA• mm2) was accomplished along with an area-normalized small signal figure of merit (IFOMSA) of 1.42M, 236k and 23.6k kHz •pF/(nA•mm2) for the DIGOTA, ST-DIGOTA and FI-DIGOTA, respectively, where the first two topologies surpass the current state of the art.

As the demand for secure Internet of Things (IoT) devices increases, the need for hardware security solutions has become more critical, particularly in applications with strict power and area constraints. Thin-film transistors (TFTs) are an emerging technology, that enables the integration of complex circuits onto thin, flexible substrates offering both low-cost manufacturing and compatibility with large-area system implementations. This paper, presents, to the best of the authors’ knowledge, the first true random number generator (TRNG) based on jittered oscillator sampling, implemented in 600 nm Indium-Gallium-Zinc-Oxide (IGZO) TFT flexible integrated circuits (FlexICs) technology.The proposed TRNG achieves a throughput of 1.33 Mbits/s, an energy consumption of 4.68 nJ/bit, and occupies an area of 0.920 mm2. The TRNG showed promising results by passing 8 NIST (National Institute of Standards and Technology) randomness tests under nominal conditions. This opens new opportunities for embedding security primitives in flexible electronics, allowing for integration of hardware security in wearable electronics, biomedical devices, communication tags and other applications.

Abstract Low cost video sensors used for streaming video signals to help firefighters, require high bit rate due to uncompressed images. To increase spectral efficiency given a limited bandwidth, very high order constellations in high signal to noise ratio regimes can be used. However, noise is not the only factor effecting the high order constellations. These constellations are also sensitive to hardware impairments and system non‐linearities. Therefore, in this paper, the effect of carrier frequency offset (CFO) on the performance of an orthogonal frequency division multiplexing (OFDM) system with high order quadrature amplitude modulation (QAM) is studied. A closed form expression is derived for the maximum normalized residual CFO that an OFDM system with M ‐QAM constellation can resist to have an error free symbol detection. Finally, the suitability of common previous CFO estimation techniques such as the cyclic prefix based technique and the Moose technique in these systems are investigate. The results show that the maximum residual CFO that an OFDM system with M ‐QAM constellation can resist is proportional to the inverse of . The results also show that very large order QAM constellations such as 4096‐QAM are very sensitive to even small residual CFO values and their performance degrades, significantly. However, the bit error rate analysis indicate that the Moose CFO estimation technique can be used in these systems to compensate the CFO effect, accurately.

The paper describes evaluation of drain current harmonics in a MOS transistor operating in moderate inversion and strong saturation. The dependence of the drain current on the gate-source and drain-source voltages is described using a simplified “reconciliation” model developed by Y. Tsividis. Then, in the proposed model the current components corresponding to the terms depending exponentially on normalized gate-source and/or drain-source modulating sinusoidal voltage are evaluated using modified Bessel functions. This approach allows one to omit the small-signal requirement for modulating signals, and calculate the first, second and third harmonics of the drain current caused by the gate-source or drain-source voltages and also find the intermodulation terms. The results are applied to the design of low-distortion low-voltage amplifiers. The recommendations are confirmed by simulations.

Full-duplex wireless communication systems are capable of transmitting and receiving signals in the same band. An important performance indicator of full-duplex systems is the amount of uncanceled self-interference, a.k.a. residual self-interference. This work investigates the distribution of the residual self-interference (SI) power in an analog post-mixer canceler. First, we focus on the impact of the SI channel coherence time on the distribution of the residual SI power and we analyze in detail the impact of the phase-noise caused by the up/down-conversion oscillators. The results achieved in this study confirm that the coherence time of the SI channel strongly impacts the distribution of the residual SI power. Considering a SI Rayleigh channel, we show that the residual SI power only follows a Gamma distribution in the limit case, when the coherence time tends to infinity (time-invariant channel). This work is the first step to understand the stochastic properties of the residual SI power, which is an important feature when digital-domain cancellation is jointly adopted with analog-domain cancellation to account for the estimated effects of the propagation channel.

We present a generic model for Multiple Phase Ring Oscillators (MPRO) with 2nphases, and derive equations for frequency, phase and phase error under the simplifying approach of injecting the error in a single element. Extensive Monte Carlo simulations, at transistor level, for the four and eight phase circuits, are in accordance with these assumptions. These results are validated by two prototype integrated circuits, implemented in a 130 nm CMOS technology: The first prototype, which is a standalone four phases Ring Oscillator (RO), validates the theoretical analysis concerning the non-linear model main conclusions and, the second prototype, which is an eight phase RO, incorporated as a block of an ISM receiver, validates the generic model for CRO concept.

A new transistor model is used for design of two LDO regulators using a differential stage loaded by a current amplifier and the voltage feedback. The first LDO has a constant bias current, the second LDO has an additional adaptable bias circuit controlled by the load current. The LDOs are analyzed and compared. When the load is absent, the transistors in both circuits are operating in weak inversion; when the load is increasing the pass transistors in both circuits are moving to strong inversion. It is shown that in these LDOs the output voltage may be higher than the input reference voltage at very small load currents, and the circuits start “to follow” the input voltage only being loaded with a load current depending on the bias and LDO loop gain. The circuits were designed for 130 nm CMOS technology and their operation was verified using CADENCE simulation tool.

In this paper we present a balun low noise amplifier (LNA) in which the noise figure (NF) and power consumption are reduced by using a feedback biasing structure. The circuit is based on a conventional wideband balun LNA with noise cancellation. We propose to replace the typical current source of the CG stage by a transistor that establishes a feedback loop in that stage. This adds a degree of freedom which can be used to vary the CG transistor's transconductance, making it different from the typical value of 20 mS. Thus. we can increase the ratio between the gm of the CG and CS stages, which reduces the LNA NF, area, and power consumption, when compared with conventional circuits. Simulation results, with 65 nm CMOS transistors at 1.2 V supply, show that the LNA bandwidth is 3.4 GHz, the voltage gain is 21.8 dB, and the NF is less than 2.5 dB, with IIP3 above -5 dBm. The power dissipation is 4.3 mW. Another design, concerning linearity, has 18.6 dB voltage gain, NF below 2.9 dB and IIP3 above +3 dBm, over a 5 GHz bandwidth, with power consumption of 8.5 mW.

The paper describes calculation of the first, second and third harmonics of the output voltage in a MOS transistor stage operating in moderate inversion (common source stage is taken as an example). The dependence of drain current on the gate-source voltage is approximated on the basis of “reconciliation” model proposed by Y. Tsividis and using the term corresponding to saturation operation. Then, the definition of moderate inversion is introduced considering a special series expansion for the function ln2(x). To simplify the calculations we consider the first two terms only for this expansion. Then the harmonic coefficients are obtained by routine calculations. The results of calculations were verified by simulations. The results are in a reasonable agreement; in particular, the presence of the zero value for the third harmonic is confirmed both in calculations and simulations.

In this paper a four-stage self-biased voltage-controlled oscillator (VCO) is presented. The proposed ring-oscillator circuit employs a combination of dynamic-threshold-MOS (DT-MOS) and bulk-driven transistors to design low-voltage low-power VCO with high oscillation frequency. By using an auxiliary body-driven latch, the VCO achieves a wide operating frequency range from 0.88 to 1.36 GHz (more than 40% tuning range). Simulation results in a 65-nm CMOS technology shows frequency variations of 3% against temperature variation of -20 °C to 85 °C, with only 0.36 mW power consumption using a 0.7 V supply voltage.

The development of new mobile communications systems faces several important challenges, namely demanding for high bit rates, high spectral efficiency, low energy consumption and the usage of hostile channels. In order to fulfill these requirements for block-based single carrier transmissions, we propose to use high order QAM constellations combined with envelope control Magnitude Modulation (MM) techniques and bit-interleaved coded modulation with LDPC codes. Also, the receiver uses powerful MM specialized IB-DFE solutions to combat the channel distortion and noise. The obtained results have shown significant improvements in terms of energy efficiency and bit error rate.

This paper describes the analysis and design of a light barrier system as a multi-subject undergraduate lab project for undergraduated students. This project allows the students to consolidate their knowledge and skills regarding analog signal processing and oscillator design. Since the project has a practical application it is also useful to motivate the students towards enjoying electronic circuit design. The system proposed here is composed of a relaxation oscillator driving a LED in the transmitter and a photo diode followed by a TIA and a bandpass filter in the receiver.

CMOS RC oscillators have low area, can be built with a low cost technology, and have a wide tuning range, but they have higher phase-noise than LC oscillators. This can be overcome by synchronizing the oscillator by injection-locking with an low phase-noise external source. We present here an experimental study of injection-locking in an RC two-integrator oscillator. First and second harmonic injection in different locations of the oscillator are investigated. A test circuit was fabricated using a standard CMOS technology with 1.2 V supply. Measurement results show that a phase noise improvement of more than 30 dB, can be obtained with only -30 dBm injected signal between 100 kHz and 10 MHz frequency offset over a wide frequency range (600 MHz to 3 GHz).

RC oscillators have lower cost and higher tuning range than LC oscillators. However, their phase noise performance is poor and in the case of the relaxation oscillator it is also far from the theoretical optimum. In this paper we present a new circuit of a quadrature relaxation oscillator with faster switching and high amplitude output signal to improve the FoM. The sizing of a prototype in a 130nm CMOS technology was done using a genetic algorithm tool. Simulation results show that the quadrature oscillator operating at 2.4 GHz achieves a figure of merit of -165 dBc/Hz.

This paper presents a new technique for the design of receiver architectures, based on the use of variable reference voltages in ADCs. The main goal is to improve the SNDR of a receiver chain when compared to traditional architectures like Low-IF or Subsampling, while performing down-conversion without the need of a Mixer block. The proposed technique takes advantage of the inherent capability of the ADC to perform the multiplication operation. High-level model simulations show that this technique is capable of improving the SNDR by about 5 dB (from 50 to 55 dB), while avoiding out-of-band noise aliasing, when compared to the referred techniques.

This paper proposes a very simple and innovative self-biasing (SB) scheme to be applied to classic fully-differential current starved (CS) ring oscillators. Using the proposed SB circuit, it is possible to reduce, simultaneously, phase-noise and temperature sensitivity of the oscillation frequency. Simulation results from a CS and from the new SB ring oscillator, both designed in a 65 nm 1.2V standard CMOS technology are presented, to validate and demonstrate the efficiency of the proposed new self-biasing scheme. These simulation results show an improvement of about 4 dB in phase-noise (at 1 MHz offset) and, at the same time, it has been verified that the oscillation frequency changes less than 0.71 % (less than 57 ppm/°C), in the temperature range ranging from -40 to 85 °C. Moreover, due to the low noise and low power design, the proposed new SB ring oscillator achieves a simulated figure-of-merit (FOM) of -163.5 dBc/Hz, which represents 8 dB improvement, accomplishing one of the best results when compared with the state-of-the art.

In this paper we present a balun LNA with gain adjustable continuously by a voltage. The LNA is based on the combination of a common-gate and a common-source stage to cancel the noise and distortion of the common-gate stage. To obtain higher gain with the same DC voltage drop we replace resistors by PMOS transistors. This also allows continuous gain control and we show that by proper design, the effect on IIP3 and IIP2 can be neglected. With this approach, we avoid the use of switches, and the input impedance and the noise figure are not affected. Simulation results with a 130 nm CMOS technology show that the balun LNA has gain continuously tunable between 12 and 20 dB. The NF is below than 3.2 dB and the best IIP3 is higher than 0 dBm and the maximum IIP2 is 14 dBm. The total power dissipation is only 4.8 mW for a bandwidth of 5 GHz.

A quadrature oscillator based on two RC oscillators with capacitive coupling is proposed and analyzed. The capacitive coupling has the advantages of being noiseless and not increasing the power dissipation. Simulation results show that the oscillation frequency increases proportionally to the coupling capacitances, which is the opposite of what happens in capacitive coupled LC oscillators. Measurements on a 130 nm CMOS circuit prototype validate the theory of the coupling mechanism. The phase-noise is −115 dBc/Hz @ 10 MHz offset, and the FoM is −155.3 dBc/Hz, which is comparable to the best state-of-the art RC oscillators, yet the dissipated power is about four times less.

The estimation of inter-channel mismatches in time-interleaved analog-to-digital converters (TI-ADCs) is a crucial step towards the compensation of output errors inherent of these converters. In this paper, we investigate a fast, accurate and low-complexity method for estimation of static gain and sample-time mismatches. The proposed technique uses a calibration signal generated on-chip through a sinusoidal oscillator inserted into a phase-locked loop (PLL), similarly as the sampling clock signal is usually generated in these high speed conversion systems. We synchronize these two PLLs to allow efficient frequency domain computations, without resorting to windowing, from which accurate estimations are feasible. We show that the accuracy of the method is not affected by nonidealities in the calibration signal as long as the calibration frequency is carefully selected.

We present a new RC relaxation oscillator with pulse self biasing, to reduce power consumption, and with harmonic filtering and resistor feedback, to reduce phase-noise. A circuit prototype in the hundreds of MHz range, designed in a 130 nm CMOS technology has a very low phase-noise, -132.6 dBc/Hz @ 10 MHz offset, and the power consumption is only 1 mW, which leads to a figure of merit (FOM) of -159.1 dBc/Hz.

This paper describes the design of a discrete-time passive Mixer/IIR filter. The use of an improved MOS Parametric Amplification leads to a moderate gain in the signal path and improved noise performance, instead of the conversion loss inherent to passive mixers. Simulation results demonstrate that, employing the proposed MPA structure based on a modified double-complementary topology with floating terminals, an improvement of over 4 dB in the overall circuit gain and up to 2 dB in the noise figure can be achieved.

In this paper we present a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed IQ ADCs with moderate resolutions. The proposed system can be fully integrated with the ADC and, besides a low-jitter clock reference, no other external high quality generators are required. A locked system comprising a first phase-locked loop (PLL) with two IQ linear outputs and a second PLL with a squared output signal are proposed as well as the dedicated voltage-controlled oscillator (VCO) circuits. To illustrate the simplicity of the proposed solution, the system is designed, parameterized and simulated targeting the BIST of a 6-bit 1 GS/s ADC.

This paper presents the implementation of a coarse-grained magnetic RAM based reconfigurable array. The reconfigurable array architecture is organized as a one-dimensional array of programmable ALU, with the configuration bits stored in magnetic random-access memories. The use of MRAM technology to implement run-time reconfigurable hardware devices is a very promising technological solution because MRAM can provide non-volatility with cell areas and access speeds comparable to those of SRAM, and with lower process complexity than flash memory. This type of coarse-grained array, where each reconfigurable element computes on 4-bit or larger input words, is more suitable to execute data-oriented algorithms and is more able to exploit larger amounts of operation-level parallelism than common fine-grained architectures. By substantially reducing the overhead for configurability, this coarse-grain architecture is also more apt to efficiently exploit run-time reconfiguration and therefore to take advantage of multi-context MRAM-based configuration memories.

We present a combined LNA-mixer circuit with low area and low power, for the 2.4 GHz ISM band. The circuit has two versions: one has an output RC low-pass filter suitable for low IF frequencies; the other has an output LC band-pass filter suitable for medium IF frequencies. Circuits, with IF of 50 MHz and 400 MHz, were designed using UMC 0.13 mum CMOS technology and 1.2 V supply, and dissipate approximately 7.6 mW.

This paper considers two oscillators (van der Pol or Robinson type) synchronized using capacitive coupling. Equations are derived for the oscillation frequency and amplitudes. They show that the frequency of synchronous oscillation is different from the frequencies of individual oscillators. The amplitudes of oscillation are also different: one oscillator becomes a master and the second oscillator becomes a slave. A method of quasilinear approximation is used to evaluate the stability of synchronous oscillation. Simulation results for a 5 GHz oscillator confirm the theoretical analysis.

Contrary to what happens with LC oscillators, the increase of coupling in cross-coupled relaxation RC-oscillators leads to a lower quadrature error and lower phase-noise. We present a 2.4 GHz CMOS quadrature relaxation oscillator, and show the measurements confirming this property. Increasing the coupling block gain, the oscillator phase-noise is reduced from -97 dBc/Hz to -104 dBc/Hz @ 1 MHz. The quadrature error is reduced from 4.3deg to 0.8deg. These results show that RC quadrature oscillators may be a practical alternative for RF transceiver applications.

It is shown that synchronization is similar to amplitude stabilization: both mechanisms involve creation of harmonics and frequency reduction. Synchronization of LC-oscillators can be achieved using similar synchronizing circuits in each oscillator connected in parallel with the tank. The output of the first synchronization circuit is routed to the second oscillator and vice versa. This scheme provides coupling using first, third and other odd harmonics. In addition, introducing coupling between common mode outputs of the synchronizing circuits provides second and other even harmonic coupling. This type of coupling may be also used between common mode outputs of amplitude stabilization circuits. The benefits of using simultaneous first and second harmonic coupling were verified designing a low-power, low phase noise 5 GHz LC oscillator with quadrature outputs. The oscillator phase noise is lower than -121.2 dBc/Hz at 1-MHz offset over the tuning range with a power consumption of 1.8 mW achieving a FOM lower than -192.2 dBc/Hz

In this paper, an IQ oscillator/mixer circuit is presented in which the mixers are an integral part of the oscillator. The oscillator alone has accurate quadrature outputs, even in the presence of component mismatch. This precise quadrature is preserved when mixers are incorporated in the oscillator. An oscillator/mixer core for a carrier frequency of 5 GHz, suitable for a low-IF front-end, was designed and tested. The power consumption is 30 mW from a 2.5 V supply, and a phase error of 1deg was measured

A new coupling mechanism is used to synchronize two Van der Pol oscillators. This coupling uses the second harmonic appearing in common mode current of each oscillator. The common mode current is measured by a current mirror, and is amplified by a current amplifier. The amplifier introduces negative feedback, so that the current in the current mirror measuring diode of the first oscillator is nearly equal to the common mode current of the second oscillator, hence the coupling is established. It is shown that the system of two oscillators is described by two differential equations where the coefficients in one equation have the perturbations defined by the second oscillator, and vice versa. The coupling amplifier gain is defined. The developed concepts are demonstrated on a 5 GHz CMOS LC oscillator with quadrature outputs. The oscillator phase noise is lower than -116 dBc/Hz at 1-MHz offset