Recent studies of silent data errors (SDEs) in mega-scale datacenters indicate that SDEs are caused by small delay defects that escaped detection by manufacturing tests or occurred during the lifetime of the system. A small delay defect is detected by a test that propagates a transition through one of the longest paths that includes the defect site. Once the path is selected, for every gate or cell on the path, ATPG assigns off-path input values to enable the propagation of a transition through the path. For complex gates, such as AOI and XOR, there are multiple sets of possible assignments (or input stimuli) that the ATPG can use, with substantially different propagation delays. Existing test generation procedures do not consider these differences in propagation delays once a path is selected. We propose a new approach to ATPG for small delay defects, called Timing Verification Test or TVT, that selects the off-path input values to maximize the delay of the path. The tests produced by TVT result in path delays that are significantly higher than those obtained when off-path input values are selected arbitrarily by the ATPG if they are not mandated by the propagation conditions. TVT also considers different PVT corners that affect the selection of the longest paths. Experimental results for an industrial core show that TVT increases the path delays by up to 15.91% for a set of the longest paths needed to detect small cell-aware delay faults at different PVT corners.

This paper describes a novel methodology of creating scan-based at-speed structural patterns to analyze and validate functional critical paths on latch-based high performance CPU cores. Silicon data comparison with traditional transition fault patterns and functional patterns are conducted and reported to illustrate the effectiveness of the proposed scheme.

GPGPU, general-purpose computing on graphics processing units, has been witnessed growing from a niche to a mainstream computing paradigm in the last decade. It is widely deployed in machine learning, artificial intelligence, and many scientific applications. In this article, we study gate-level logic simulation for scan test patterns, one of the key algorithmic components for test generation, fault grading and design rule check. We are exploring if GPGPU can deliver scalable performance speedup as promised by its massive parallelism. We discuss the limitations of the state of art work. With GPUs' architectural features in mind, a novel algorithm of hybrid race-tolerant parallel logic simulation is proposed to unleash its immense power of parallelization. Its unique integration of oblivious simulation and event-driven simulation leads to a scalable realization of parallel logic simulation for scan patterns. For the first time in the literature, it is demonstrated that a modest GPU can handle an industrial design of over twenty million gates with excellent performance scalability.

This paper presents the structural testing challenges for Intel's high-performance IA Cores and the novel ATPG solutions developed to overcome them. Intel's IA Cores employ a design structure which, poses unique testing challenges for industry-standard design-for-testing (DFT) tools. First, the prevalent use of both latches and flip-flops while employing a two-phase clocking scheme. Second, the structural-based patterns reuse the functional clock network, hence keeping the performance and power profile similar to that of a functional test. Such design properties introduce unique Automatic-Test-Pattern-Generation (ATPG) challenges. The paper will introduce the innovative enhancements to the Design Rule Checks (DRCs), developed to handle these unique designs.

Diagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group, used as the “candidate set of scan cells for the next round of ANN inference,” will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.

General-purpose computing on graphics processing units (GPGPUs) is a programming model that uses graphics cards to perform computations traditionally done by CPU. It began to become practical with the advent of programmable shaders and floating-point support on GPU in around 2001. The spread of GPGPU has been accelerated with introduction of CUDA from NVIDIA in 2006 and later OpenCL in 2009. Nowadays GPGPU is widely deployed in various applications, such as data mining, artificial intelligence, and many scientific computations. GPGPU seemingly promises immense parallelism with massive concurrent cores, and thus much shorter run times. This is true for algorithms that bear intrinsic data and task parallelism, such as image and video processing. For an ATPG system where some algorithms are sequential in nature, the speedup is not easy to achieve in the real world. Flaws in setting up speedup evaluation can lead to false promises. Will GPGPU-based ATPG system become a reality? Or it is just a myth. In this paper, we try to provide an answer by surveying state-of-the-art works and by analyzing practical aspects of today's industrial designs.

Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process incorporating ANNs with gradually refined focuses. Experimental results on benchmark circuits show that this method is, on average, 20% more accurate than a state-of-the-art commercial tool for intermittent stuck-at faults, and improves the hit rate from 25.3% to 73.9% for some test-case.

Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.

The paper summarizes practical logic structures creating race and/or glitch conditions which can cause incorrect test patterns. First, the design rule check (DRC) is proposed to identify such structures. Next, a novel methodology is proposed to handle such problematic structures during test generation to ensure the correctness of the test patterns with minimum test coverage loss. The proposed solution can seamlessly integrated into the automatic low coverage analysis to evaluate the test coverage impact and determine the root cause of major test coverage loss.

Achieving very high test coverage (e.g. 99.9% stuck-at fault model) is becoming a standard for ICs used in the high reliable systems like automotive vehicle. X-sources (unknown value sources) are one of the common root causes preventing designs from achieving the test coverage goal. The paper first summarizes common X-sources in industry designs. A novel approach is then proposed to systematically identify and analyze all of the X-sources that impacts the test coverage most with accurate estimation by utilizing the Automatic Test Pattern Generator (ATPG). Consequently, users are able to take the analysis result and make necessary and minimum changes to eliminate Xs to achieve the test quality goal effectively.

A clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel flush test procedure to determine if a clock network has any small delay faults. This method does not require any change of the clock network, but it does require a “special test clock signal,” which can be generated on the chip by using only standard cells. Experimental results of transistor-level simulation on benchmark circuits injected with resistive open defects in the layout show that the proposed method is capable of detecting a delay fault as small as 52.8 ps.

Timing exceptions (e.g. false and multicycle paths) are commonly applied to optimize the performance and meet timing requirements. These timing exceptions are presented as extra constraints during test generation to ensure the correctness of the pattern set. Without considering the impact on test quality, timing exceptions often result in unpredictable test coverage impact. This paper proposes a systematic approach involving both the design and test phases to achieving high test quality while meeting the design timing requirements.

A clock network in a 3D-IC is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, studies have shown that small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel test method to determine if a clock network has any small delay faults. This method does not require any change of the clock network, and it is capable of detecting a delay fault as small as 50ps through outlier analysis, while locating the FFs affected by the fault.

In today's multi-die ICs, the die-to-die interconnects are often complicated and susceptible to various kinds of manufacturing defects and stress-induced performance degradation in the field. This phenomenon has prompted a need to perform online monitoring of the signal integrity over the die-to-die interconnects for reliability critical applications. In this work, we present a slack-time binning scheme so that one can constantly quantify the margin of a timing failure threat (TFT) occurring to a registered die-to-die interconnect. The proposed scheme attaches a Slack-Time Monitor (ST-monitor) to each Flip-Flop (FF) that receives a signal transmitted through a die-to-die interconnect under monitoring. Two techniques are introduced to enhance the traditional “Timing-Violation Checker”, namely (1) a tunable guard-band technique, and (2) an offset compensation technique. With these two techniques, one can perform online slack-time binning. Experimental results using a 90nm CMOS process show that the proposed scheme has a low area overhead of only approximately 2.35 times the area of a boundary scan cell.

Interconnects are sophisticated in a multi-die IC using integration technology such as interposer or Wafer-Level Packaging (WLP), and thus they could become vulnerable to early lifetime failure or aging. Our previous work in [12] provides a way to monitor the delay of a TSV non-intrusively by a transition time binning procedure. However, it is not suitable for longer interconnects in an interposer or in the Re-Distribution Layer (RDL) of a WLP-packaged IC, as the cost could become prohibitively high due to large area overhead. To overcome this limitation, we propose a new scheme in this paper by incorporating a Distributed Time-to-Digital Converter (d-TDC). Experimental results indicate that such a scheme can support on-line delay monitoring for long interconnects, while having an area overhead equivalent to 2 boundary scan cells only for each interconnect.

Die-to-die interconnects linking multiple functional dies in a modern 3-D or 2.5-D IC by micro-bumps could experience resistance increase after certain time of field operation due to parametric defects or aging. To cope with this reliability threat, we present an “on-line transition-time binning method” that aims to continuously detect excessive transition time occurring at a target die-to-die interconnect. Our method attaches a monitor to the termination end of each target interconnect. Any transition (rising or falling) is converted into a pulse-width first, which is then further compared to a dynamically tunable threshold for a binary pass/fail judgment. By multiple runs of transition-time monitoring while sweeping the threshold incrementally, the “transition-time bin” of each target interconnect can be derived and thereby a timing failure threat can be detected by a monitor center before it actually strikes.

A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a number of distinct features. First, it can target not only catastrophic faults, but also timing faults. Second, it can be applied to general multi-pin interconnects and it can be applied to repair an interposer with multiple faulty interconnects. Third, it can perform the test-and-then-repair flow on-the-fly, and thereby eliminating the overhead of extra repair storage incurred in previous methods.

Through Silicon Vias (TSVs) are known to be susceptible to various thermal-mechanical and electro-migration effects that could lead to unexpected resistance increase after certain time of field operation. To cope with this reliability threat, we present an on-line monitoring method that aims to continuously detect excessive transition time occurring to a TSV (which often indicates performance degradation). Our method attaches a monitor to the termination end of a TSV. Any transition there is converted into a pulse-width, which is further compared to a dynamically tunable threshold. A Timing Failure Threat (TFT) is thereby detected when the pulse-width exceeds the threshold. This method can be applied to a large number of TSVs easily since the monitoring results are binary and can be stored in FFs forming a scan chain for easy access.

The continuously increasing complexity and size of the modern high performance design often introduces the testability barriers which either restrict the desirable test quality, or require extended test generation time. To detect such testability barriers and accurately estimate the test coverage quickly is important to minimize the risk of test quality issue or any later stage design change. The paper proposes a novel technique to efficiently estimate the deterministic test coverage for large designs. The test coverage estimation with less than 0.5% error can be achieved with more than 30X run time reduction compared to the test generation run time of the entire fault population.

Interposer is a critical component in a 2.5-D IC as it serves as a common platform upon which multiple known good dies are bonded. Any defect in an interposer will lead to a loss of compound yield. To avoid such a last-minute yield loss, we propose a timing-aware Built-In Self-Repair method to increase the fault tolerance of high-speed interposer wires. The most unique feature of our method as compared to previous works is that ours can repair not only catastrophic faults, but also timing faults. We present an on-the-fly test-and-repair flow that can seamlessly link Pulse-Vanishing Test, a previous timing-aware interconnect test method, with a popular redundancy structure.

This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Second, our method can also be used to characterize the propagation delay across each fault-free interposer wire.

In this paper, we present a general at-speed test method for die-to-die interconnects and demonstrate its particular application to the interposer wires in a 2.5-D IC. At the heart of this method is a pulse-vanishing test technique (called PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the driver end. If this pulse vanishes at the receiver's output, then it indicates the presence of a delay fault. This PV-test technique is effective for detecting not only resistive open faults, but also resistive bridging faults between interposer wires. This method has several other advantages. For example, the implementation is especially easy as it incorporates only logic cells and can be merged with boundary scan cells. Also, it can support on-the-spot diagnosis which is desirable in applications where subsequent built-in self-repair is needed.

Testing the quality of the interposer wires in a 2.5-D stacked IC can avoid the penalty arising from bonding known-good dies to a defective interposer. However, an interposer is particularly hard to test alone due to the lack of a device layer. This paper addresses this problem by proposing amid-bond test method - in which the interposer is tested after each die is attached to the substrate. We borrow the technique of pre-bond test method for the TSV and enhance it by a length-normalization scheme to cope with interposer wires of diverse wire lengths. Simulations show that this mid-bond test method can catch a high percentage of open faults before subsequent dies are attached.

Multicycle paths are commonly seen in today's high performance designs with multi-frequency clock domains. Previous methods either treat the multicycle paths as false paths and masking the transition on the paths, or slow down the clocks in order to test the multicycle paths. Both approaches would compromise the at-speed test quality. In this paper, we present an at-speed test methodology to target the faults on the multicycle paths using the same clock scheme as regular faults at the single cycle paths. The methodology takes SDC files which defines all timing exceptions and the clock frequency information and create at-speed pattern set that detects faults on both single and multicycle paths. The approach also handles all of the timing exceptions and constraints defined in SDC to prevent simulation mismatches. The experiment results on couple industrial designs demonstrate the effectiveness and efficiency of the proposed methodology to handle complex designs with large timing exception paths.

Testing the speed of post-bond interposer wires in a 2.5-D stacked IC is essential for silicon debugging, yield learning, and even for fault tolerance. In this paper, we present a novel at-speed test technique called Pulse-Vanishing test (PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the d river end. If the pulse signal can successfully propagate through the interposer wire and reach the other end, then the interposer wire is considered fault-free. Otherwise, it indicates the presence of a delay fault. This new test technique has several technical merits. For example, the Design-for-Testability (DfT) circuit for an interposer wire is similar to the boundary scan cell and can be controlled through scan chain. Also, it can be easily adapted to perform at-speed Built-In Self-Test (BIST) supporting on-the-spot diagnosis.

Delay testing and characterization of interposer wires in a 2.5-D stacked IC is essential for yield learning and silicon debug. This paper addresses this problem by proposing a data analysis flow for perturbation-based oscillation test method to cope with the various wire-lengths of the interposer wires. With the proposed method, one can not only detect small delay faults but also characterize the delay across each fault-free interposer wire.

The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed to handle the design with such rule violations to prevent simulation mismatches while minimizing the test coverage lost.

Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) the ability to handle both the resistive open fault and the leakage fault in the same test structure; 2) a capability that allows an user to have a better measure of the severity of the fault; and 3) an all-digital and easy to implement design-for-testability circuit.

Leakage tests have been a challenge for through-silicon vias (TSVs) in a 3-D IC. Most existing methods are still inadequate in terms of the range of testable leakage currents. In this paper, we borrow the wisdom of the IO-pin leakage test while enhancing it with two features. First, we make it more suitable for a TSV, which has a much smaller capacitance than an IO pin. Second, we support a wide range of leakage test (e.g., from 0.125 μA to 16 μA), and thereby allowing for flexible test threshold setting and leakage characterization. To achieve this goal, we present two sets of techniques-1) wait-time generation by programmable delay line, and 2) wait-time propagation with a self-timed timing control scheme to overcome the timing skew problem due to signal routing. We demonstrate that the entire scheme can be done in only logic gates, making it easy to integrate into the common design flow.

A parametric delay fault could arise in a through-silicon via (TSV) of a 3-D IC due to a manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield-learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the output of a TSV from a normal inverter to a Schmitt-Trigger inverter, the parametric delay fault on the TSV can be characterized and detected. SPICE simulation reveals that this technique remains effective even when there is significant process variation. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32768 TSVs when the test clock is running at 10 MHz.

Leakage test has been a challenge for TSVs in a 3D IC. Most existing methods are still inadequate in terms of the range of leakage currents they can test. In this work, we borrow the wisdom of the IO pin leakage test while enhancing it with two features: (1) we make it more suitable for TSVs which has a much smaller capacitance than an IO pin, and (2) we support leakage binning in a wide range of currents from 1 uA to 128 uA, and thereby allowing flexible test threshold settings and leakage characterization. Since we use only logic gates in the Design-for-Testability circuit, it is also easier to be integrated into the TSV design flow than previous methods.

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.

A TSV in a 3D IC could suffer from two major types of parametric faults — a resistive open fault, or a leakage fault. Dealing with these parametric faults (which do not destroy the functionality of a TSV completely but only degrade its quality or performance) is often trickier than dealing with a stuck-at fault. Previous works have not proposed a unified test structure and method that can characterize their respective effects. Based on our previous test structure, called VOT (Variable Output Threshold) scheme for delay faults, we propose a unified in-situ characterization flow for both parametric fault types of a post-bond TSV. With this flow, one can easily derive a more insightful assessment of a parametric fault in production test, process monitoring, and/or diagnosis-driven yield learning.

For two-pattern at-speed scan testing, the excessive power supply noise at the launch cycle may cause the circuit under test to malfunction, leading to yield loss. This paper proposes a new weight assignment scheme for logic switching activity; it enhances the IR-drop assessment capability of the existing weighted switching activity (WSA) model. By including the power grid network structure information, the proposed weight assignment better reflects the regional IR-drop impact of each switching event. For ATPG, such comprehensive information is crucial in determining whether a switching event burdens the IR-drop effect. Simulation results show that, compared with previous weight assignment schemes, the estimated regional IR-drop profiles better correlate with those generated by commercial tools.

Speedpath debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speedpath debug based on functional patterns can be very expensive. In this paper, we explore scan-based speedpath debug techniques based on at-speed scan test patterns. Several enhancements are implemented to improve over an earlier proposed scan-based speedpath diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high performance microprocessor design.

Recently, multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) system with space-frequency block coding (SFBC) has attracted substantial attention because of its robustness toward time selective fading channel. However, SFBC MIMO-OFDM system needs the same number of inverse fast Fourier transforms (IFFTs) as the number of antennas at the transmitter and the computational complexity is extremely high. In addition, it also inherits the disadvantage of a high peak-to-average power ratio (PAPR) from OFDM technique. In this paper, a low-complexity transmitter architecture is proposed for SFBC MIMO-OFDM systems with a general encoding matrix and an arbitrary number of transmitter antennas. The proposed scheme fully exploits the time-domain signal properties and requires only one IFFT. Then, a PRPR reduction scheme is presented by using the proposed transmitter architecture. The PAPR reduction performance of the proposed scheme is slightly worse than that of the traditional selected mapping (SLM) scheme. However, the proposed scheme achieves a substantially lower computational complexity.

Analysis of power grid IR-drop during scan test application has drawn growing attention because excessive IR-drop may cause a functionally correct device to fail at-speed testing. The analysis is challenging since the power grid IR-drop profile depends on not only the switching cells locations but also the power grid structure. This paper presents a scalable implementation methodology for quantifying the IR-drop effects of a set of switching cells. An example of its application to guide power-safe scan pattern generation is illustrated. The scalability and effectiveness of the proposed quantitative measure is evaluated with a 130 nm industrial design with 800 K cells.

Extraordinary power consumption during the scan test may inadvertently cause a functional good die to fail. This paper proposes a peak power reduction algorithm for the scan test which considers both the shift cycles and capture cycles simultaneously to limit the peak power of all test cycles during the test generation. In addition, the analysis also recommends the types of circuit structures that are more suitable to add test logic for maximum power reduction with the minimum test cost. The proposed methodology is highly efficient and can be applied to large industrial designs.

An at-speed scan test methodology is proposed for the purpose of the timing optimization and calibration. The proposed method, called TOC-ATPG, addresses both undertesting and overtesting issues of the traditional at-speed scan-based structural test. A pseudo-random pattern-based circuit analysis is first applied to analyze the potential glitches and transitions due to the functional illegal states. A list of state elements to be constrained during ATPG to prevent the sensitization of the functional illegal transitions and glitches are derived. During ATPG the derived constraints are applied to prevent overtesting, and timing-aware transition fault approach is used simultaneously to detect the fault through the timing critical paths to overcome the undertesting issue. The proposed method demonstrates very high correlation to the purely sequential test in functional mode with bounded run time overhead and can be applied to very large design.

Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using at-speed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique.

With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay-fault diagnosis problem and propose a novel approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower-than-nominal clock frequencies. We evaluate the utility ofn-detection and timing-aware automatic-test-pattern-generated (ATPG) sets. Experimental results show that using timing-aware ATPG sets yields better diagnostic resolution and results in better delay-defect-size estimations compared ton-detection ATPG sets. We experimentally determined our diagnosis algorithm's sensitivity to delay variations.

With nanometer processes, at-speed testing is required to filter out failing chips with delay defects to ensure high product quality. Locating delay defects is important not only for improving yield but also providing important information to enhance at-speed test methods to meet quality goals. In this paper, a method that leverages successful static defect diagnosis method to diagnose delay defects is presented. To avoid missing any defect suspects, transition fault model is used with special considerations of self masking, glitch detection and passing bit mismatch. The effectiveness of this approach is demonstrated with simulation experiments as well as two case studies on failing chips from Renesas Technology's 130nm process.

This paper describes a robust scan pattern mismatch debugger for the scan pattern validation process. Simulation mismatches observed during scan pattern validation process need to be resolved before scan pattern can be used in silicon. In this framework, we use efficient structural cone to create VCD values from a timing-based simulator. The VCD values are then used to trace the mismatches from failing observation points to the mismatch sources. Root-cause analysis is then performed by combining all mismatch source instances to conclude the most likely mismatch reasons. Comparing to existing solutions, the proposed mismatch debug flow doesnpsilat require VCD values of all signals in the designs, nor does it require multiple simulation of the test patterns in the Verilog simulator. Experimental results show the effectiveness and efficiency of the proposed scan pattern mismatch debug flow.

With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design-timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify delay faults that require nonrobust test patterns due to incorrect emulation of the failure analyzer's behavior. We propose a novel approach to performing delay-fault diagnosis for robust and nonrobust tests. We enhance the diagnostic resolution by utilizing passing patterns, processing failure logs at various slower frequencies, and applying n-detection and timing-aware automatic test pattern generation sets. Experimental results show that our approach can diagnose delay faults with good resolution. The algorithm is stable with respect to delay variations that manufactured chips might experience.

Generating test patterns without considering timing exceptions and constraints can lead to invalid test responses, resulting in false failures on the tester or yield loss. A path-oriented approach to handle timing exception paths with setup violations during at-speed test generation has been presented in [1]. This paper presents a unified and complete algorithm for computing test responses in the presence of timing exceptions with both setup and hold violations, and Boolean timing constraints. The new algorithm analyzes all possible effects of glitches in the circuit. It resolves pessimism in the case of multiple interacting timing exception paths. The new method significantly reduces the number of unknowns in the test responses, resulting in improved test coverage and test compression. The new method can be applied to 1) any fault model, 2) any test pattern, 3) any simulation environment, and/or 4) any test generator.

A test methodology for the control signals including clock logic, ripple reset and register file read/write control of the Cortex-A8trade high performance microprocessor core is presented. The target fault models include the stuck-at fault, transition fault and hold time fault models.

In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in (Vorisek et al., 2006). The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism

In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs

With feature sizes shrinking, manufacturing defects and parameter variations often cause design timing failures. Crosstalk coupling is one of such causes. It is essential that timing failures be correctly and quickly diagnosed. The authors present a methodology to diagnose the delay-defect in presence of crosstalk, given the physical information such as crosstalk coupling capacitance, neighborhood information and SDF delay information. The authors provide diagnosis results for 180, 130, 90 and 65 nm technologies

As electronic design feature sizes continue to shrink and clock speeds continue to rise, more and more companies have turned to at-speed test techniques to help ensure high test and product quality. Due to incomplete timing information during automatic test pattern generation (ATPG), it is possible that some at-speed patterns may activate paths which are not required to meet system speed, and these patterns may fail during production test. It is often difficult and time consuming to identify these paths manually. This paper describes how to use diagnosis techniques to automatically identify these paths. Using this approach, the authors found most of these paths were false or multicycle paths inside DFT logic. These could be fixed by enhancing the timing exception paths used during ATPG to mask out transition values through these paths. Elimination of these paths resulted in a 300 MHz increase in the speed of the transition fault test pattern. However, occasionally the authors did find some failing paths were real functional problems and design changes were needed to resolve them

As electronic design feature sizes continue to shrink and clock speeds continue to rise, more and more companies have turned to at-speed test techniques to help ensure high test and product quality. An important piece of the design flow is static timing analysis (STA), which is used to verify the timing of paths in the design. Part of the STA process is to specify false and multicycle path exceptions to relax the timing for these paths for synthesis and layout purposes. This paper explains the importance of using these timing path exceptions during automatic test pattern generation (ATPG) and compares previous methods of handling these paths to a new innovative method that provides higher test and product quality.

In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time.

A scan circuit construction obviates ATPG constraints for the prevention of tristate contention on internal tristate busses and one-hot muxes. The circuit is supported by enhanced ATPG.

Diagnosis of scan test fail data plays a crucial role in enhancing ramp up of new CMOS technology generations. To enable faster feedback it is preferable to establish a monitoring diagnosis methodology on the production test floor. This paper reports result of a study on using test time optimized compressed scan technology and associated new algorithms for fault diagnosis. Data is based on a system-on-a-chip (SoC) product that is manufactured using Infineon Technologies' 130 nm process. A comparison with uncompressed scan test and diagnosis shows feasibility of implementing a monitoring diagnosis flow with compressed scan test serving the high throughput test flow.

In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. Unfortunately, the resolution of the existing delay-fault diagnostic methodologies is still unsatisfactory. In this paper, the feasibility of using the circuit timing information to guide the delay-fault diagnosis is investigated. A novel and efficient diagnostic approach based on the delay window propagation (DWP) is proposed to achieve significantly better diagnostic results than those of an existing delay-fault diagnostic commercial tool. Besides locating the source of the timing errors, for each identified candidate the proposed method determines the most probable delay defect size. The experimental results indicate that the new method diagnoses timing faults with very good resolution.

In scan test environment, designs with embedded compression techniques can achieve dramatic reduction in test data volume and test application time. However, performing fault diagnosis with the reduced test data becomes a challenge. In this paper, we provide a general methodology based on circuit transformation technique that can be applied for performing fault diagnosis in the context of any compression technique. The proposed methodology enables seamless reuse of the existing standard ATPG based diagnosis infrastructure with compressed test data. Experimental results indicate that the diagnostic resolution of devices with embedded compression is comparable with that of devices without embedded compression.

In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this work, we analyze failures caused by the hold-time-violations. We investigate the feasibility of using circuit-timing information to guide the hold-time-fault diagnosis. We propose a novel and efficient diagnostic approach based on timing window propagation. For each identified candidate, our method locates the source of the hold-time violation and determines the most probable defect size. Experimental results indicate that the new method diagnoses hold-time related defects with very good resolution.

Growing ASIC design sizes and advanced deep sub-micron technologies require new fault models and more test vectors to meet high test quality goals. To realize these goals within given test resources and cost constraints, new DFT techniques must be used. This paper reports test quality metrics and the test cost of industrial designs for different fault models using three DFT techniques: ATPG for deterministic patterns, Logic BIST for pseudo-random patterns, and EDT for compressed deterministic patterns. It is shown how these techniques can be used to achieve the high quality goals within the test resources currently available for stuck-at tests.

We study the relationship between multiple fault diagnosability and fault detection count. Instead of developing a complex diagnostic algorithm for multiple fault behavior, we change the test sets used in test and diagnosis. This allows us to apply a simple single-fault based diagnostic algorithm, and yet achieve very good diagnosability for the failure test cases caused by multiple faults. We have verified experimentally the effectiveness of n-detection tests for multiple-fault cases and explained the results in probabilistic terms.

This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects. Volume data obtained by testing a production ASIC with these new multiple-detect patterns shows increased defect screening capability and very good agreement with the bridging coverage estimated by the ATPG tool. 1.

In this paper, we analyze failing circuits and propose a multiple-fault diagnosis approach. Our methodology has been validated experimentally and has proved to be highly efficient and effective in diagnosing multiple faults. We do not consider the multiple-fault behavior explicitly, but rather use an incremental simulation-based approach to diagnose failures one at a time. Furthermore, to improve the diagnosability, we propose a failing-primary-output partitioning algorithm. Experimental results show that our approach has approximately linear time complexity, and it achieves high diagnosability and resolution. Our approach has also been validated on data collected from manufactured chips. The diagnosis time is within minutes for real industrial chips that failed because of multiple faults. 1.

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

In this paper, we introduce a hierarchical test set structure called star test, derived from the experimental observation of the fault clustering phenomena. Based on the concept of star test, two applications are studied: one applied to built-in-self-test (BIST); the other to automatic test pattern generation (ATPG). First, a very high quality and low-cost BIST scheme, named STAR-BIST is proposed. Experimental results have demonstrated that a very high fault coverage can be obtained without any modification of the logic under test, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. Second, an efficient test generator, named STAR-ATPG, is developed which speeds up the ATPG performance by a factor of up to five for large industrial circuits.

This paper presents a new scan-based BIST schemewhich achieves very high fault coverage without the deficienciesof previously proposed schemes. This approach utilizes scan orderand polarity in scan synthesis, effectively converting the scanchain into a ROM capable of storing some "center" patterns fromwhich the other vectors are derived by randomly complementingsome of their coordinates. Experimental results demonstrate that avery high fault coverage can be obtained without any modificationof the mission logic, no test data to store and very simple BISThardware which does not depend on the size of the circuit.

This paper presents an improved scan-based BIST scheme which achieves very high fault coverage without any modification of the mission logic, i.e. no test point insertion, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. The approach utilizes scan order and its polarity in scan synthesis, effectively converting it into a ROM encoding a few test vectors which serve as centers of clusters from which the other vectors are derived by complementing at random their coordinates. The proposed method successfully tests the random pattern resistant faults, which is the major problem of traditional LFSR-based BIST, with lower hardware cost and a more efficient algorithm than previous methods. Experimental results demonstrate that a very high fault coverage can be achieved with much smaller test set than other pseudorandom pattern generation methods published so far.