String-number conversion is an important class of constraints needed for the symbolic execution of string-manipulating programs. In particular solving string constraints with string-number conversion is necessary for the analysis of scripting languages such as JavaScript and Python, where string-number conversion is a part of the definition of the core semantics of these languages. However, solving this type of constraint is very challenging for the state-of-the-art solvers. We propose in this paper an approach that can efficiently support both string-number conversion and other common types of string constraints. Experimental results show that it significantly outperforms other state-of-the-art tools on benchmarks that involves string-number conversion.

In an IVN system, electronic components are connected and communicated through multiple protocols subjected to different requirements. In practice, intelligent vehicles need to exchange data between the body control subsystem and the chassis control subsystem, usually involving both the controller area network (CAN) protocol and the FlexRay protocol. In such a system, delays and congestion of frame transmissions are more likely to happen, leading to safety issues. In this paper, following a two-stage strategy, we managed to find an appropriate abstraction to model the IVN system in the presence of both protocols. Based on the abstraction, we proposed a framework for modeling and verifying IVN systems in their design phase using timed model checking techniques. To analyze the timed properties of communications, we chose the UPPAAL as the platform. Regarding concerns of reusability, this framework was structured in such a way that it is adaptable to IVN systems with different topologies. This framework was validated by checking the communication behaviors against the protocol specifications. We constructed design models with three typical topologies and estimated the response time of frames. The reusability of this framework over different topologies was demonstrated by comparing the estimated response times against the corresponding topological characteristics.

The Vienna Development Method (VDM) is a formal method that supports modeling and analysis of software systems at various levels of abstractions. For a model specified by the VDM specification language (VDM-SL), the correctness of the model relies on discharging the proof obligations (POs), especially in the case of implicit specifications. In this paper, we propose an approach that encodes and discharges POs of VDM-SL models using SMT solvers. More specifically, POs generated by the Overture tool are encoded and discharged in the Z3 SMT solver. Our case studies showed that the approach can discharge significant part of proof obligations of a VDM-SL model efficiently.

In order to nd a clue to effectively introducing and utilizing new technology in improving software development process, we analyze and visualize the in-degree centrality of the process area networks in terms of the related process areas in CMMI-DEV. By visualizing the results of in-degree centrality analysis, we can have a perspective of process improvement in using advanced technology.

This paper presents results on formal verification of high-speed cryptographic software. We consider speed-record-setting hand-optimized assembly software for Curve25519 elliptic-curve key exchange presented by Bernstein et al. at CHES 2011. Two versions for different microarchitectures are available. We successfully verify the core part of the computation, and reproduce detection of a bug in a previously published edition. An SMT solver supporting array and bit-vector theories is used to establish almost all properties. Remaining properties are verified in a proof assistant with simple rewrite tactics. We also exploit the compositionality of Hoare logic to address the scalability issue. Essential differences between both versions of the software are discussed from a formal-verification perspective.

With the growing demands for automotive auxiliary functions, more and more complex applications have been developed based on OSEK/VDX OS. However, how to check the developed applications is becoming a challenge for developers. Although some invaluable formal methods have been proposed to check actual software, these methods cannot be directly employed to check OSEK/VDX applications. In this paper, we describe and develop an approach to check OSEK/VDX applications using SMT-based bounded model checking. We also implement a prototype tool and conduct many experiments on several examples. The experiment results show that our approach can completely check the properties associated with (i) variables, (ii) mutual exclusion, (iii) service API, and (iv) tasks execution sequences of developed applications.

Recently, the capacity of flash-memory storage systems has grown rapidly, and flash-memory technology has advanced along with the wave of consumer electronics and embedded systems. In order to properly manage product cost and initialization performance, vendors face serious challenges in system design and analysis. Thus, the timing analysis of system initialization and crash recovery for a segment-based flash translation layer has become an important research topic. This article focuses on system initialization, crash recovery, and timing analysis. The timing analysis of system initialization involves the relationship between the size of the main memory and the system initialization time. The timing analysis of crash recovery explains the worst case recovery time. The experiments in this study show that the timing analysis of system initialization and crash recovery can be applied to the segment-based flash translation layer.

This paper proposes a different approach for service adaptation which aims to: (i) support non-regular adaptation; (ii) integrate adaptation and model checking. First, a pushdown automaton is used to model the adaptor so that non-regular languages are possible. Second, behavior interfaces of services are modeled by Büchi automata in order to take the advantage of the acceptance condition. By defining the property of ”behavior mismatch free” in a LTL formula using acceptance condition, the detection of behavior mismatches is performed by model checking. Also, the adaptor generation is performed by model checking of pushdown systems with the guidance of a special over-behavioral adaptor called “coordinator”. Then the returned counterexample is converted to a pushdown automaton, the expected adaptor.

While the capacity of flash-memory storage systems keeps increasing significantly, an effective and efficient management of flash-memory space has become a critical design issue. Different granularities in space management impose different management costs and mapping efficiency. In this paper, we will explore an address translation mechanism (AddrTM) that can dynamically and adaptively switch between different granularities in the mapping of logical block addresses into physical block addresses in flash-memory management. The objective is to provide high performance in address mapping and space utilization and, at the same time, to have the main memory requirements, the garbage collection overhead, and the system initialization time under proper management. The experimental results show that the proposed adaptive mechanism can provide better performance improvement and practicability than other well-known coarse-grained management mechanisms over realistic workloads.