Noise-shaping successive approximation register (NS-SAR) ADCs combine high resolution with energy efficiency, but their performance degrades at bandwidths in the tens of MHz due to limited oversampling ratios (OSR) and adoption of low-order passive filters. This work introduces a$3{^{\text {rd}}}$-order NS-SAR ADC that leverages a multi-input amplifier and a multi-input comparator, enabling independent optimization and flexible filter coefficient sizing. In addition, a ratio-based floating inverter amplifier ensures remarkable gain stability across process, voltage, and temperature (PVT) variations. Implemented in a 28-nm CMOS process, the prototype achieves 12.3-ENOB over a 20-MHz bandwidth while consuming 1.56 mW, resulting in a Schreier figure-of-merit (FoMS) of 177-dB with robust and consistent performance across PVT corners.

The paper presents a detailed analysis of phase noise in periodically switched oscillators (PSOs) which are emerging as effective multipliers in mmW applications. The analysis shows that the output phase noise of these stages cannot be estimated using the analogy to retimed oscillators. Closed form expressions for the transfer of both the reference and the oscillator noise are derived together with a correction to include the contribution of the oscillator close-in phase noise. The results are validated against Cadence Spectre RF® simulations of a PSO designed in a 28-nm bulk CMOS technology. The excess noise arising from the finite duration of the on-off transients is also discussed.

This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115$\mu \text{s}$, overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL.

The paper presents a generalization of the Groszkowski's result in differential oscillators, providing novel equations to describe the oscillation frequency dependence on the harmonic content. The effect of the common-mode oscillation is rigorously included. Moreover, an additional term, arising from the dependence of the transistor current on the drain voltage, which is dominant any time ohmic operation occurs, is disclosed here for the first time. This framework is applied to Van der Pol oscillators, both nMOS and CMOS, designed in a 28-nm bulk CMOS technology. The results correctly match the oscillation frequency dependence derived from detailed circuit simulations. The analysis shows that, when even harmonics are relevant, the classical Groszkowski's result is not able to account for close-in phase noise performance. The novel theoretical framework fully justifies, instead, the simulation results and sheds new light on the flicker noise up-conversion mechanisms in the considered oscillator structures.

A novel low-power and wide-locking-range divide-by-three injection-locked frequency divider with single inductor is presented in this paper. The classical topology with divide-by-two locking scheme is improved via the introduction of an extra tail-injection driven by the central node of the floating-source direct injector. This new concept is applied to the design of a 15GHz divider-by-three in a standard 65-nm LP CMOS technology, which reaches, in post-layout simulations at 100° C temperature, a 23.6% locking range at an input power of 0dBm and DC power consumption of 1.56mW. The divider figure of merit together with the compact size of only 0.09mm2are best in class for injection-locking dividers with single inductor and same input power. The figure of merit is also very close to the values reached by the best injection-locking dividers-by-three, that, however, use more inductors.

This paper discusses the impact of CMOS scaling in the design and performance of switched-capacitor power amplifiers operating in the sub-GHz bands for Internet-of-Things applications. While the peak drain efficiency is found to improve by about 10% when the amplifier is scaled down from a 65-nm standard CMOS to a 28-nm fully-depleted SOI CMOS process, the average efficiency instead slightly degrades. Moreover, it is theoretically demonstrated that the power density (peak-power over area-occupation) is a function of the supply voltage and the dielectric constant of the switched capacitor insulator and it is about 13% higher in the 65-nm CMOS node.

The adoption of the digital/time converter (DTC) circuit has improved the performance of ΔΣ fractional-N phase-locked loops (PLLs). Accurate cancellation of ΔΣ quantization error via the DTC requires an automatic calibration made by an LMS loop. A high-order ΔΣ speeds up calibration convergence and improves PLL spectral purity, though at the price of larger quantization error and wider DTC range. To overcome this problem, we propose an innovative parallel segmentation scheme which reduces the range of quantization error without compromising spectral purity and convergence speed. The effectiveness of the proposed segmentation scheme is demonstrated via behavioral-level simulations of a digital PLL and compared to the conventional cascaded segmentation scheme.

This paper reviews the recent historical trends of the NAND Flash technology, highlighting the evolution of its main parameters and explaining what allowed it to become not only the most important integrated solution for nonvolatile storage of high volumes of data but also a strong rival eroding the market share of hard-disk drives. The scaling trend followed by planar arrays will be discussed with close attention, along with the major physical constraints impacting the performance and the reliability of modern deca-nanometer technologies. This will make clear why the development of further planar nodes with feature size below ~15 nm, representing today's state of the art, can be considered less favorable than turning all the efforts toward the integration of 3-D arrays. The most promising 3-D architectures will then be reviewed, discussing their benefits and issues and addressing the impact of the change of the integration paradigm from the standpoint of the major NAND applications.

This paper presents a digital background linearization technique for high-speed Nyquist-rate digital-to-analog Converters (DACs), based on the use of a least-mean-square (LMS) multipath adaptive filter that continuously measures and cancels non-linearity arising from static errors. In contrast to previously-published correlation-based techniques, the proposed method is not limited to the cancellation of component mismatches, but it performs the correction of the overall static characteristic regardless of the source of non-linearities. It requires only an additional low-speed accurate DAC and moderate digital hardware complexity, avoiding the need for a multibit analog-to-digital converter. The effectiveness of the proposed technique applied to a current-steering DAC suggests that it could be useful to overcome the typical high-speed DAC trade-off, allowing the elimination of static non-linearity errors without sacrificing dynamic performances.

This paper introduces a technique for suppressing the effect of deterministic jitter in phase-locked loops based on multiplying delay-locked loops. A digital loop operating in background of normal operation detects the static phase offset between the two reference-signal paths by means of a single-bit time-to-digital converter and compensates for it by means of a digital-to-time converter.

This paper describes a simulation method to compute oscillator phase noise which combines transient and periodic-transfer-function analyses, available in most of the commercial circuit simulators. The proposed calculation technique is simple to implement and provides the designer a deep insight into phase noise generation mechanisms for both stationary and cyclostationary sources, thus resulting a powerful tool to perform an optimum design in RF applications.

The mismatch-induced fractional spurs have so far limited the adoption of phase-interpolation-based fractional-N PLLs. Only recently a background cancellation technique, embedded in a digital fractional-N PLL, has faced this issue. In this paper, we will show that this technique is equivalent to a multi-path adaptive circuit that cancels the effects of the phase interpolator non-linearity. This analysis allows highlighting the speed/accuracy trade-off inherent in these algorithms. Simulation results verify the validity of the proposed approach.

VCO for wireless receivers must fulfil tight requirements of phase noise and their complete integration in silicon VLSI technologies is still an open issue due to the low quality factor of the inductors. In this paper we address some of the constraints met in the design of low noise oscillator stages: the tank topology and its quality factor, the dynamics of the transconductor stage and its loading effects, the limitation resulting from the AM-to-PM conversion.