Demo Data from EDBT 2026 / reviewers in the wild / expert
Qi Zhang 0108
dblp:52/323-108
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2022
0000-0003-0558-372XORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Cloud and datacenter computing · 87% Storage systems · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cloud and datacenter computing
datacenter network |
0.6 | 1 | 2022 | iBalancer: Load-Aware in-Server Flow Scheduling for Sub-Millisecond Tail Latency · IEEE Trans. Parallel Distributed Syst. 2022 |
Cloud and datacenter computing › quality of service
tail latency |
0.6 | 1 | 2022 | iBalancer: Load-Aware in-Server Flow Scheduling for Sub-Millisecond Tail Latency · IEEE Trans. Parallel Distributed Syst. 2022 |
Storage systems › key-value storage
in-memory key-value store |
0.2 | 1 | 2022 | iBalancer: Load-Aware in-Server Flow Scheduling for Sub-Millisecond Tail Latency · IEEE Trans. Parallel Distributed Syst. 2022 |
Methods — techniques the papers use, named apart from their topics
polling time interval metric · 0.6kernel bypass · 0.6flow-to-core binding · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | iBalancer: Load-Aware in-Server Flow Scheduling for Sub-Millisecond Tail LatencyabstractAchieving microsecond-scale tail latency poses an extreme challenge to the conventional architecture of “NIC-OS-Application” in the face of high concurrent requests. Existing kernel-bypass network systems improve this situation significantly. Still, they cannot achieve load-aware in-server requests distribution, which in turn not only harms resource efficiency but, more importantly, beats the goal of squeezing tail latency. This paper proposes iBalancer, an in-server proactive load balancer for the kernel-bypass system, which aggressively handles NIC-side flow scheduling according to the load of threads on the processor-side. Furthermore, we propose a novel metric, “polling time interval (PTI),” to quantify the load of worker threads, which not only indicates utilization of the core bound to the worker thread but also reflects the differences in the processing time of different flows. By scheduling flows according to the metric PTI, iBalancer tends to average the queueing latencies of different flows, such as Set & Get operations for an in-memory key-value store. In addition, by decoupling flow scheduling from packet steering, iBalancer achieves a tail latency aware flow-to-core binding and preserves hardware-based request distribution among cores. The proposed system is evaluated and compared to mTCP and Shenango using two representative microsecond-scale network applications: Memcached KVS and a real-time deep-learning-based financial fraud identification application. Experimental results show that iBalancer can process up to 4.75$ \times $and 1.55$ \times \ $higher load over mTCP and Shenango under 500μs 99thpercentile tail latency limit on Memcached. For the financial fraud identification application, iBalancer is able to process 4.56$ \times $and 1.16$ \times $higher load than mTCP and Shenango considering 900μs tail latency. Qi Zhang 0108, Yi Liu 0013, Tao Liu 0029 |
IEEE Trans. Parallel Distributed Syst. | 1 |