Demo Data from EDBT 2026 / reviewers in the wild / expert
Jochen Beister
dblp:52/3872
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 1982
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 61% Integrated circuit design · 26% Hardware reliability and fault tolerance · 13% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 1 | 1974 | A Unified Approach to Combinational Hazards · IEEE Trans. Computers 1974 |
Electronic design automation › hardware verification and test
hazard analysis |
0.0 | 1 | 1974 | A Unified Approach to Combinational Hazards · IEEE Trans. Computers 1974 |
Integrated circuit design
digital circuit design |
0.0 | 2 | 1974 | A Unified Approach to Combinational Hazards · IEEE Trans. Computers 1974 On the Implementation of Failure-Tolerant Counters · IEEE Trans. Computers 1968 |
Hardware reliability and fault tolerance
fault-tolerant design |
0.0 | 1 | 1968 | On the Implementation of Failure-Tolerant Counters · IEEE Trans. Computers 1968 |
Integrated circuit design › digital circuit design
combinational logic |
0.0 | 1 | 1974 | A Unified Approach to Combinational Hazards · IEEE Trans. Computers 1974 |
Integrated circuit design › digital circuit design
threshold logic |
0.0 | 1 | 1968 | On the Implementation of Failure-Tolerant Counters · IEEE Trans. Computers 1968 |
Methods — techniques the papers use, named apart from their topics
unate function · 0.0transition subcube analysis · 0.0threshold logic elements · 0.0error-correcting state assignments · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1982 | Word reduction in microprogrammed controllers by state-dependent preprocessing of the inputs
Albrecht Ditzinger, Jochen Beister |
Microprocessing and Microprogramming | 2 |
| 1974 | A Unified Approach to Combinational HazardsabstractTransients in combinational circuits are approached through an analysis of the transition process in a pure delay circuit model that completely separates delay from structure and logic. During any transition, only monotonically increasing sequences of transient input vertices can occur because no transient input variable can change more than once. This restriction to the shortest trajectories through the transition subcube yields a common criterion for all types of hazards in feedback-free combinational circuits: a transition is hazard-free iff the transient switching function is unate in the transition subcube with respect to the initial and final vertices. Jochen Beister |
IEEE Trans. Computers | 1 |
| 1968 | On the Implementation of Failure-Tolerant CountersabstractAbstract—A new method of designing and implementing intrinsically failure-tolerant counters with error-correcting state assignments is proposed. Threshold logic elements are used, and state recovery circuitry is united with the flip-flop input logic. A decimal counter built according to this method requires considerably fewer components and has a lower probability of failure at less cost than a diode logic version. Jochen Beister |
IEEE Trans. Computers | 1 |