Demo Data from EDBT 2026 / reviewers in the wild / expert
David T. Wang
dblp:52/3987
· DBLP profile ↗
7ranked-venue papers
2as first author
0since 2021 · last 1997
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 2Artificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1Human-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 2 | 1975 | Properties of Faults and Criticalities of Values under Tests for Combinational Networks · IEEE Trans. Computers 1975 An Algorithm for the Genaration of Test Sets for Conmbinational Logic Networks · IEEE Trans. Computers 1975 |
Electronic design automation › hardware test
fault detection and location |
0.0 | 1 | 1975 | Properties of Faults and Criticalities of Values under Tests for Combinational Networks · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test › test generation
single fault test sets |
0.0 | 1 | 1975 | An Algorithm for the Genaration of Test Sets for Conmbinational Logic Networks · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1975 | An Algorithm for the Genaration of Test Sets for Conmbinational Logic Networks · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test
combinational circuit testing |
0.0 | 2 | 1975 | Properties of Faults and Criticalities of Values under Tests for Combinational Networks · IEEE Trans. Computers 1975 An Algorithm for the Genaration of Test Sets for Conmbinational Logic Networks · IEEE Trans. Computers 1975 |
Methods — techniques the papers use, named apart from their topics
test set generation algorithm · 0.0fault simulation · 0.0fault property analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1997 | Two theoretical and practical aspects of knitting technique: invariants and a new class of Petri netabstractWe present two aspects of knitting technique, the structural properties (especially the P- and T-invariants), and the synchronized choice net (a new class of Petri net), that are of both theoretical importance and practical uses to the verification of structural correctness of a Petri net or to detect the structural problem of a Petri net. This work first proves that the ordinary Petri nets synthesized with knitting technique are structurally bounded, consistent, conservative and safe (when each home place holds one token) using the well-known linear algebra approach. It also provides a procedure for finding P- and T-invariants for Petri net synthesized using the knitting technique. We present examples for P-invariants and show that we can synthesize Petri nets more general than the "asymmetric-choice nets". The algorithm for finding P-invariants of ordinary Petri nets is extended to find the P-invariants for a general Petri net synthesized with knitting technique and the arc-ratio rules. We present a new class of Petri nets, called synchronized choice nets, which are the largest set of Petri nets that can be covered by both T-components and P-components. An algorithm is proposed to find its T-components and the P-components, respectively. The complexity of this algorithm is also presented. The theory of synchronized choice nets has the potential to simplify that for free choice nets. Daniel Yuh Chao, David T. Wang |
IEEE Trans. Syst. Man Cybern. Part B | 2 |
| 1994 | Extending the Knitting Technique to Petri Net Synthesis of Automated Manufacturing SystemsabstractThe modelling or synthesis of ordinary Petri nets has been recognized as a key step for applying Petri nets to performance analysis, control and simulation of industrial production systems. This paper addresses this synthesis problem by adopting a global and incremental synthesis approach: the knitting technique for manufacturing systems. The knitting technique has been applied to Petri net modelling and analysis of communication networks. The idea behind this technique is to introduce details in an incremental way, i.e. by adding new paths and/or cycles to a Petri net. At each step the Petri net model grows according to certain rules which will guarantee such system properties as boundedness, liveness and reversibility. Thus the cumbersome analysis for these properties can be avoided while designers can still build up a Petri net model for a complicated system. The knitting rules are divided into two types: TT and PP with a number of variations. This paper formulates and discusses these rules in the context of manufacturing. The theoretical results on the preservation of system properties using the proposed rules are presented. The results are illustrated through Petri net modelling of an automated manufacturing system which consists of two robots, five machines and two automatic guided vehicles. This approach is compared with other existing synthesis and its distinguishing advantages are indicated in the conclusion. Future research along this direction is also discussed. Daniel Yuh Chao, MengChu Zhou, David T. Wang |
Comput. J. | 3 |
| 1994 | An Interactive Tool for Design, Simulation, Verification, and Synthesis of ProtocolsabstractAbstract We have developed a user‐friendly CAD graphical tool for the design, verification, simulation, and synthesis of protocols based on an interactive tool for Petri net and state diagram designs. Special features of this tool are: the capability of modeling both control and data flows, reduction and analysis, simulation of network behavior and performance, coding (parametrized protocols and automatic implementation), synthesis (two party protocol and ordinary Petri nets), animation and flexible design. Since it is Petri‐net based, it allows simulation during all design phases and has extensive applications such as parallel debugging and simulation, expert systems, etc. Future enhancements of this tool are also discussed. Daniel Yuh Chao, David T. Wang |
Softw. Pract. Exp. | 2 |
| 1993 | Convergence Time and Memory Capacity of Higher-order Hopfield Associative Memory with Multi-valued NeuronsabstractWe investigate the two basic properties, i.e. convergence time and memory capacity, of the higher-order Hopfield associate memory with multi-valued neurons. The second-order Hopfield neural network of multi-valued neurons is presented analytically. The properties of the combined higher-order multi-valued model is then studied. Finally, the memory capacity of the higher-higher order binary-valued model is studied using a statistical approach. Daniel Yuh Chao, David T. Wang, D. C. Douglas Hung |
Comput. J. | 2 |
| 1992 | Enhancement Of Memory Capacity Of Neural NetworksabstractTwo approaches to enhance the memory capacity of neural networks are presented. The first approach is to break a large neural network into a number of independent subnetworks. This causes a drastic increase of the memory capacity and a reduction of the convergence time to stable states. The second approach is to use the limit cycle of states which can be employed to simulate a sequence of temporal memory states. This can also greatly increase the memory capacity without the use of higher-order terms. The searching of limit cycles for a given synaptic matrix is a very difficult problem. Analysis and synthesis of limit cycles are presented. Daniel Yuh Chao, David T. Wang |
IROS | 2 |
| 1975 | An Algorithm for the Genaration of Test Sets for Conmbinational Logic NetworksabstractAn algorithm is developed for generating a single-fault detection test set to be used in a combinational logic network. This algorithm has two unique characteristics. 1) When a test is generated, a list of faults detected by this test is available. Fault simulation, therefore, is not required after the test has been generated. 2) It generates a test set rather than a single test. Each test, with the exception of the first one, is based on a previous test. Repetition of effort and overlapped coverage of faults for different test generations are thus reduced. David T. Wang |
IEEE Trans. Computers | 1 |
| 1975 | Properties of Faults and Criticalities of Values under Tests for Combinational NetworksabstractThis correspondence discusses the properties of faults in combinational networks and their relationships with fault-detection and fault-location test sets. David T. Wang |
IEEE Trans. Computers | 1 |